• Clint Sbisa's avatar
    arm64: Enable PCI write-combine resources under sysfs · 5fd39dc2
    Clint Sbisa authored
    This change exposes write-combine mappings under sysfs for
    prefetchable PCI resources on arm64.
    
    Originally, the usage of "write combine" here was driven by the x86
    definition of write combine. This definition is specific to x86 and
    does not generalize to other architectures. However, the usage of WC
    has mutated to "write combine" semantics, which is implemented
    differently on each arch.
    
    Generally, prefetchable BARs are accepted to allow speculative
    accesses, write combining, and re-ordering-- from the PCI perspective,
    this means there are no read side effects. (This contradicts the PCI
    spec which allows prefetchable BARs to have read side effects, but
    this definition is ill-advised as it is impossible to meet.) On x86,
    prefetchable BARs are mapped as WC as originally defined (with some
    conditionals on arch features). On arm64, WC is taken to mean normal
    non-cacheable memory.
    
    In practice, write combine semantics are used to minimize write
    operations. A common usage of this is minimizing PCI TLPs which can
    significantly improve performance with PCI devices. In order to
    provide the same benefits to userspace, we need to allow userspace to
    map prefetchable BARs with write combine semantics. The resourceX_wc
    mapping is used today by userspace programs and libraries.
    
    While this model is flawed as "write combine" is very ill-defined, it
    is already used by multiple non-x86 archs to expose write combine
    semantics to user space. We enable this on arm64 to give userspace on
    arm64 an equivalent mechanism for utilizing write combining with PCI
    devices.
    Signed-off-by: default avatarClint Sbisa <csbisa@amazon.com>
    Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Acked-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: default avatarArd Biesheuvel <ardb@kernel.org>
    Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
    Cc: Bjorn Helgaas <helgaas@kernel.org>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Jason Gunthorpe <jgg@nvidia.com>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Will Deacon <will@kernel.org>
    Link: https://lore.kernel.org/r/20200918033312.ddfpibgfylfjpex2@amazon.comSigned-off-by: default avatarWill Deacon <will@kernel.org>
    5fd39dc2
pci.h 764 Bytes