• Florian Fainelli's avatar
    perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events · 7025fdbe
    Florian Fainelli authored
    The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
    up to the RC_ST_SPEC (0x91) event with the exception of:
    
    - L1D_CACHE_REFILL_INNER (0x44)
    - L1D_CACHE_REFILL_OUTER (0x45)
    - L1D_TLB_RD (0x4E)
    - L1D_TLB_WR (0x4F)
    - L2D_TLB_REFILL_RD (0x5C)
    - L2D_TLB_REFILL_WR (0x5D)
    - L2D_TLB_RD (0x5E)
    - L2D_TLB_WR (0x5F)
    - STREX_SPEC (0x6F)
    
    Create an appropriate JSON file for mapping those events and update the
    mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
    file.
    Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
    Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Mark Rutland <mark.rutland@arm.com>
    Cc: Namhyung Kim <namhyung@kernel.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Sean V Kelley <seanvk.dev@oregontracks.org>
    Cc: Will Deacon <will.deacon@arm.com>
    Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
    Link: http://lkml.kernel.org/r/20190513202522.9050-4-f.fainelli@gmail.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
    7025fdbe
mapfile.csv 734 Bytes