• Andrey Grodzovsky's avatar
    drm/amdgpu: Vega20 SMU I2C HW engine controller. · 691bac9d
    Andrey Grodzovsky authored
    Implement HW I2C enigne controller to be used by the RAS EEPROM
    table manager. This is based on code from ATITOOLs.
    
    v2:
    Rename the file and all function prefixes to smu_v11_0_i2c
    
    By Luben's observation always fill the TX fifo to full so
    we don't have garbadge interpreted by the slave as valid data.
    
    v3:
    Remove preemption disable as the HW I2C controller will not
    stop the clock on empty TX fifo and so it's not critical to
    keep not empty queue.
    Switch to fast mode 400 khz SCL clock for faster read and write.
    
    v5:
    Restore clock gating before releasing I2C bus and fix some
    style comments.
    
    v6:
    squash in warning fix, fix includes (Alex)
    Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
    Reviewed-by: default avatarLuben Tuikov <Luben.Tuikov@amd.com>
    Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
    691bac9d
amdgpu_ras_eeprom.c 14 KB