• Huacai Chen's avatar
    MIPS: Loongson: Add Loongson-3A R4 basic support · 7507445b
    Huacai Chen authored
    All Loongson-3 CPU family:
    
    Code-name         Brand-name       PRId
    Loongson-3A R1    Loongson-3A1000  0x6305
    Loongson-3A R2    Loongson-3A2000  0x6308
    Loongson-3A R2.1  Loongson-3A2000  0x630c
    Loongson-3A R3    Loongson-3A3000  0x6309
    Loongson-3A R3.1  Loongson-3A3000  0x630d
    Loongson-3A R4    Loongson-3A4000  0xc000
    Loongson-3B R1    Loongson-3B1000  0x6306
    Loongson-3B R2    Loongson-3B1500  0x6307
    
    Features of R4 revision of Loongson-3A:
    
      - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc.
      - Support variable ASID bits.
      - Support MSA and VZ extensions.
      - Support CPUCFG (CPU config) and CSR (Control and Status Register)
          extensions.
      - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way
          set-associative).
    
    Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is
    the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/
    2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors
    which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R
    (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in
    general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G.
    Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
    Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
    Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: James Hogan <jhogan@kernel.org>
    Cc: linux-mips@linux-mips.org
    Cc: linux-mips@vger.kernel.org
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Cc: Huacai Chen <chenhuacai@gmail.com>
    7507445b
c-r4k.c 51.7 KB