• Bruce Allan's avatar
    e1000e: workaround invalid Tx/Rx tail descriptor register write · c6e7f51e
    Bruce Allan authored
    When the Manageability Engine (ME) is enabled on 82579, it periodically
    accesses some MAC CSR registers.  There is an arbiter in hardware which
    prevents simultaneous access of these registers by the host software, i.e.
    the driver.  There is a hardware bug in the aribter that signals a host
    access of the registers later than it actually happens.  A write of the
    Transmit or Receive Descriptor Tail register could result in an incorrect
    value if the driver and ME perform simultaneous accesses which could result
    in an access to an invalid memory address.  This would return an
    Unsupported Request which could hang the hardware.  Workaround the issue by
    checking the FWSM register bit24 which is set by ME before it accesses the
    MAC CSR registers.
    Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
    Tested-by: default avatarJeff Pieper <jeffrey.e.pieper@intel.com>
    Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
    c6e7f51e
ich8lan.c 111 KB