• Anup Patel's avatar
    irqchip/sifive-plic: Implement irq_set_affinity() for SMP host · cc9f04f9
    Anup Patel authored
    Currently on SMP host, all CPUs take external interrupts routed via
    PLIC. All CPUs will try to claim a given external interrupt but only
    one of them will succeed while other CPUs would simply resume whatever
    they were doing before. This means if we have N CPUs then for every
    external interrupt N-1 CPUs will always fail to claim it and waste
    their CPU time.
    
    Instead of above, external interrupts should be taken by only one CPU
    and we should have provision to explicitly specify IRQ affinity from
    kernel-space or user-space.
    
    This patch provides irq_set_affinity() implementation for PLIC driver.
    It also updates irq_enable() such that PLIC interrupts are only enabled
    for one of CPUs specified in IRQ affinity mask.
    
    With this patch in-place, we can change IRQ affinity at any-time from
    user-space using procfs.
    
    Example:
    
    / # cat /proc/interrupts
               CPU0       CPU1       CPU2       CPU3
      8:         44          0          0          0  SiFive PLIC   8  virtio0
     10:         48          0          0          0  SiFive PLIC  10  ttyS0
    IPI0:        55        663         58        363  Rescheduling interrupts
    IPI1:         0          1          3         16  Function call interrupts
    / #
    / #
    / # echo 4 > /proc/irq/10/smp_affinity
    / #
    / # cat /proc/interrupts
               CPU0       CPU1       CPU2       CPU3
      8:         45          0          0          0  SiFive PLIC   8  virtio0
     10:        160          0         17          0  SiFive PLIC  10  ttyS0
    IPI0:        68        693         77        410  Rescheduling interrupts
    IPI1:         0          2          3         16  Function call interrupts
    Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
    Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
    Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    cc9f04f9
irq-sifive-plic.c 7.55 KB