• Guennadi Liakhovetski's avatar
    i.MX31: Image Processing Unit DMA and IRQ drivers · 5296b56d
    Guennadi Liakhovetski authored
    i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
    Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
    Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
    (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
    CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
    and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
    supported over dmaengine and irq-chip APIs respectively.
    
    IDMAC is a specialised DMA controller, its DMA channels cannot be used for
    general-purpose operations, even though it might be possible to configure
    a memory-to-memory channel for memcpy operation. This driver will not work
    with generic dmaengine clients, clients, wishing to use it must use
    respective wrapper structures, they also must specify which channels they
    require, as channels are hard-wired to specific IPU functions.
    Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
    Signed-off-by: default avatarGuennadi Liakhovetski <lg@denx.de>
    Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
    5296b56d
ipu_idmac.c 45 KB