[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this

[How]
DCE6 targets are added replicating existing DCE8 implementation.

NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits

(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
     updated dce60 due to following kernel 5.0 commits:
     24f7dd7e ("drm/amd/display: move pplib/smu notification to dccg block")
     9566b675 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
     4244381c ("drm/amd/display: clean up base dccg struct")
     4c5e8b54 ("drm/amd/display: split dccg clock manager into asic folders")
     84e7fc05 ("drm/amd/display: rename dccg to clk_mgr")
     77f6916a ("drm/amd/display: Remove duplicate header")
     9f7ddbea ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
     4ece61a2 ("drm/amd/display: set clocks to 0 on suspend on dce80")

(v3b) updated dce60 due to following kernel 5.1 commits:
     380604e2 ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
     32e61361 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
     1877ccf6 ("drm/amd/display: Change from aux_engine to dce_aux")
     c69dffab ("drm/amd/display: fix eDP fast bootup for pre-raven asic")

(v4b) updated dce60 due to following kernel 5.2 commits:
     e5c41970 ("drm/amd/display: Add plane capabilities to dc_caps")
     813d20dc ("drm/amd/display: Fix multi-thread writing to 1 state")
     ea36ad34 ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
     afcd526b ("drm/amd/display: Add fast_validate parameter")

(v5b) updated dce60 due to following kernel 5.3 commits:
     e7e10c46 ("drm/amd/display: stop external access to internal optc sync params")
     78cc70b1 ("drm/amd/display: Engine-specific encoder allocation")
     dc88b4a6 ("drm/amd/display: make clk mgr soc specific")
     4fc4dca8 ("drm/amd: drop use of drmp.h in os_types.h")

(v6b) updated dce60 due to following kernel 5.4 commits:
     54a9bcb0 ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
     9adc8050 ("drm/amd/display: make firmware info only load once during dc_bios create")

(v7b) updated dce60 due to following kernel 5.5 commits:
     cabe144b ("drm/amd/display: memory leak")
     8276dd87 ("drm/amd/display: update register field access mechanism")
     f6040a43 ("drm/amd/display: configurable aux timeout support")
     bf7f5ac3 ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")

(v8b) updated dce60 due to following kernel 5.6 commits:
     d9e32672 ("drm/amd/display: cleanup of construct and destruct funcs")
     f42ea55b ("drm/amd/display: add separate of private hwss functions")

(v9b) updated dce60 due to following kernel 5.8 commits:
     bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
     904fb6e0 ("drm/amd/display: move panel power seq to new panel struct")
     d4caa72e ("drm/amd/display: change from panel to panel cntl")

(v10) Fix up PLL handling for DCE6:
     DCE6.0 supports 2 PLLs.  DCE6.1 supports 3 PLLs. (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>