• Chris Wilson's avatar
    drm/i915: Share per-timeline HWSP using a slab suballocator · 8ba306a6
    Chris Wilson authored
    If we restrict ourselves to only using a cacheline for each timeline's
    HWSP (we could go smaller, but want to avoid needless polluting
    cachelines on different engines between different contexts), then we can
    suballocate a single 4k page into 64 different timeline HWSP. By
    treating each fresh allocation as a slab of 64 entries, we can keep it
    around for the next 64 allocation attempts until we need to refresh the
    slab cache.
    
    John Harrison noted the issue of fragmentation leading to the same worst
    case performance of one page per timeline as before, which can be
    mitigated by adopting a freelist.
    
    v2: Keep all partially allocated HWSP on a freelist
    
    This is still without migration, so it is possible for the system to end
    up with each timeline in its own page, but we ensure that no new
    allocation would needless allocate a fresh page!
    
    v3: Throw a selftest at the allocator to try and catch invalid cacheline
    reuse.
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Cc: John Harrison <John.C.Harrison@Intel.com>
    Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190128181812.22804-4-chris@chris-wilson.co.uk
    8ba306a6
i915_drv.h 110 KB