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Ralf Baechle authored
commit 9cdf30bd upstream. Returns a non-zero value if the current processor implementation requires an IHB instruction to deal with an instruction hazard as per MIPS R2 architecture specification, zero otherwise. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> [bwh: Backported to 3.2: trim the CPU type list] Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
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