• Satheeshakrishna M's avatar
    drm/i915/skl: Implementation of SKL display power well support · 94dd5138
    Satheeshakrishna M authored
    This patch implements core logic of SKL display power well.
    
    v2: Addressed Imre's comments
    	- Added respective DDIs under power well #1 and #2
    	- Simplified repetitive code in power well programming
    
    v3: Implemented Imre's comments
    	- Further simplified power well programming
    	- Made sure that PW 1 is enabled prior to PW 2
    
    v4: Fix minor conflict with the the cherryview support (Damien)
    
    v5: Add the PLL power domain to the always on power well (Damien)
    
    v6: Disable BIOS power well (Imre)
        Use power well data for comparison (Imre)
        Put the PLL power domain into PW1 as its needed for CDCLK (Satheesh,
        Damien)
    
    v7: Addressed Imre's comments
      - Lowered the time out to 1ms
      - Added parantheses in macro
      - Moved debug message and fixed wait_for interval
    
    v8:
      - Add a WARN() when swiching on an unknown power well (Imre, done by Damien)
      - Whitespace fixes (spaces instead of tabs) (Damien)
    
    v9: (Imre, done by Damien)
      - Merge the register definitions with this patch
      - Merge the MISC IO power well in this patch
    
    v10: (Imre, done by Damien)
    
      - Define the Misc I/O power domains to be the power well 1 ones as Misc I/O
        needs to be enabled with PW1
      - Added Transcoder A and VGA domains to PW 2
      - Remove the MISC_IO power domains as well in the the always on
        domains definition
      - Move Misc I/O power well at the top of the power well list so it's turned
        on right after PW1.
    Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
    Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v3,v6,v7)
    Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    94dd5138
intel_runtime_pm.c 45.7 KB