-
Junzhi Zhao authored
Currently, the code sets the "pll" to the desired multiple of the pixel clock manully(4*3m 8*3,etc). The valid range of the pll is 1G-2G, however, when the pixel clock is bigger than 167MHz, the "pll" will be set to a invalid value( > 2G), then the "pll" will be 2GHz, thus the pixel clock will be in correct. Change the factor to make the "pll" be set in the (1G, 2G) range. Signed-off-by:
Junzhi Zhao <junzhi.zhao@mediatek.com> Signed-off-by:
Bibby Hsieh <bibby.hsieh@mediatek.com>
0d220079