• Weinan Li's avatar
    drm/i915/gvt: init mmio by lri command in vgpu inhibit context · cd7e61b9
    Weinan Li authored
    There is one issue relates to Coarse Power Gating(CPG) on KBL NUC in GVT-g,
    vgpu can't get the correct default context by updating the registers before
    inhibit context submission. It always get back the hardware default value
    unless the inhibit context submission happened before the 1st time
    forcewake put. With this wrong default context, vgpu will run with
    incorrect state and meet unknown issues.
    
    The solution is initialize these mmios by adding lri command in ring buffer
    of the inhibit context, then gpu hardware has no chance to go down RC6 when
    lri commands are right being executed, and then vgpu can get correct
    default context for further use.
    
    v3:
    - fix code fault, use 'for' to loop through mmio render list(Zhenyu)
    
    v4:
    - save the count of engine mmio need to be restored for inhibit context and
      refine some comments. (Kevin)
    
    v5:
    - code rebase
    
    Cc: Kevin Tian <kevin.tian@intel.com>
    Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
    Signed-off-by: default avatarWeinan Li <weinan.z.li@intel.com>
    Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
    cd7e61b9
scheduler.c 37 KB