• Peter Zijlstra's avatar
    perf_counter: Fix up P6 PMU details · 9c74fb50
    Peter Zijlstra authored
    The P6 doesn't seem to support cache ref/hit/miss counts, so
    we extend the generic hardware event codes to have 0 and -1
    mean the same thing as for the generic cache events.
    
    Furthermore, it turns out the 0 event does not count
    (that is, its reported that on PPro it actually does count
    something), therefore use a event configuration that's
    specified not to count to disable the counters.
    Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
    LKML-Reference: <new-submission>
    Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
    9c74fb50
perf_counter.c 45.2 KB