Some xHCI host controllers may have optional support for Latency
Tolerance Messaging (LTM).  This allows USB 3.0 devices that support LTM
to pass information about how much latency they can tolerate to the xHC.
A PCI xHCI host will use this information to update the PCI Latency
Tolerance Request (LTR) info.  The goal of this is to gather latency
information for the system, to enable hardware-driven C states, and the
shutting down of PLLs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>