• Ville Syrjälä's avatar
    drm/i915: Trick CL2 into life on CHV when using pipe B with port B · b0b33846
    Ville Syrjälä authored
    Normmally the common lane in a PHY channel gets powered up when some
    of the data lanes get powered up. But when we're driving port B with
    pipe B we don't want to enabled any of the data lanes, and just want
    the DPLL in the common lane to be active.
    
    To make that happens we have to temporarily enable some data lanes
    after which we can access the DPLL registers in the common lane. Once
    the pipe is up and running we can drop the power override on the data
    lanes allowing them to shut down. From this point forward the common
    lane will in fact stay powered on until the data lanes in the other
    channel get powered down.
    
    Ville's extended explanation from the review thread:
    
    On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
    > One Q, why only for port B? Port C is also in same common lane right?
    
    Port B is in the first PHY channel which also houses CL1. CL1 always
    powers up whenever any lanes in either PHY channel are powered up.
    CL2 only powers up if lanes in the second channel (ie. the one with
    port C) powers up.
    
    So in this scenario (pipe B->port B) we want the DPLL from CL2, but
    ideally we only want to power up the lanes for port B. Powering up
    port B lanes will only power up CL1, but as we need CL2 instead we
    need to, temporarily, power up some lanes in port C as well.
    
    Crossing the streams the other way (pipe A->port C) is not a problem
    since CL1 powers up whenever anything else powers up. So powering up
    some port C lanes is enough on its own to make the CL1 DPLL
    operational, even though CL1 and the lanes live in separate channels.
    Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
    [danvet: Amend commit message with extended explanation.]
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    b0b33846
intel_drv.h 48 KB