• Rasmus Villemoes's avatar
    irqchip: Add support for Layerscape external interrupt lines · 0dcd9f87
    Rasmus Villemoes authored
    The LS1021A allows inverting the polarity of six interrupt lines
    IRQ[0:5] via the scfg_intpcr register, effectively allowing
    IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
    check the type, set the relevant bit in INTPCR accordingly, and fixup
    the type argument before calling the GIC's irq_set_type.
    
    In fact, the power-on-reset value of the INTPCR register on the LS1021A
    is so that all six lines have their polarity inverted. Hence any
    hardware connected to those lines is unusable without this: If the line
    is indeed active low, the generic GIC code will reject an irq spec with
    IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
    disable the polarity inversion (writing 0 to the relevant bit) before
    unmasking the interrupt.
    
    Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature,
    just with a different number of external interrupt lines (and a
    different POR value for the INTPCR register). This driver should be
    prepared for supporting those by properly filling out the device tree
    node. I have the reference manuals for all three boards, but I've only
    tested the driver on an LS1021A.
    
    Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on
    arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol
    which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set.
    Signed-off-by: default avatarRasmus Villemoes <linux@rasmusvillemoes.dk>
    Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20191107122115.6244-3-linux@rasmusvillemoes.dk
    0dcd9f87
irq-ls-extirq.c 4.31 KB