• Josh Boyer's avatar
    [POWERPC] 4xx: Workaround for CHIP_11 Errata · 13c501e6
    Josh Boyer authored
    The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that
    causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction
    requests that cross the end-of-memory-range boundary.  Since the DDR
    controller only returns the valid portion of a read request, the bridge
    will prevent other PLB masters from completing their transactions.
    
    This implements the recommended workaround for this errata for chips that
    use older versions of firmware that do not already handle it.  The last
    4KiB of memory are hidden from the kernel to prevent the problem
    transactions from occurring.
    Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
    Acked-by: default avatarStefan Roese <sr@denx.de>
    Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
    13c501e6
4xx.c 15.2 KB