• Paul Mackerras's avatar
    [POWERPC] Fix MMIO ops to provide expected barrier behaviour · f007cacf
    Paul Mackerras authored
    This changes the writeX family of functions to have a sync instruction
    before the MMIO store rather than after, because the generally expected
    behaviour is that the device receiving the MMIO store can be guaranteed
    to see the effects of any preceding writes to normal memory.
    
    To preserve ordering between writeX and readX, and to preserve ordering
    between preceding stores and the readX, the readX family of functions
    have had an sync added before the load.
    
    Although writeX followed by spin_unlock is not officially guaranteed
    to keep the writeX inside the spin-locked region unless an mmiowb()
    is used, there are currently drivers that depend on the previous
    behaviour on powerpc, which was that the mmiowb wasn't actually required.
    Therefore we have a per-cpu flag that is set by writeX, cleared by
    __raw_spin_lock and mmiowb, and tested by __raw_spin_unlock.  If it is
    set, __raw_spin_unlock does a sync and clears it.
    
    This changes both 32-bit and 64-bit readX/writeX.  32-bit already has a
    sync in __raw_spin_unlock (since lwsync doesn't exist on 32-bit), and thus
    doesn't need the per-cpu flag.
    
    Tested on G5 (PPC970) and POWER5.
    Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
    f007cacf
io.h 14.7 KB