• Vladimir Oltean's avatar
    ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect · c7861adb
    Vladimir Oltean authored
    Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
    But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC
    are pointing towards the same internal PCS. Therefore nobody is
    controlling the internal PCS of eTSEC0.
    
    Upon initial ndo_open, the SGMII link is ok by virtue of U-boot
    initialization. But upon an ifdown/ifup sequence, the code path from
    ndo_open -> init_phy -> gfar_configure_serdes does not get executed for
    the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII
    link remains down for eTSEC0. On the LS1021A-TWR board, to signal this
    failure condition, the PHY driver keeps printing
    '803x_aneg_done: SGMII link is not ok'.
    
    Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match
    mdio1 device.
    
    Fixes: 055223d4 ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR")
    Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
    Reviewed-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
    Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
    Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
    c7861adb
ls1021a.dtsi 26 KB