• Paul Walmsley's avatar
    OMAP3 clock: add a short delay when lowering CORE clk rate · c9812d04
    Paul Walmsley authored
    When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
    divider, add a short delay before returning to SDRAM to allow the SDRC
    time to stabilize.  Without this delay, the system is prone to random
    panics upon re-entering SDRAM.
    
    This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
    room temperature, 64 loops seems to work okay; so add another 32 loops for
    environmental and process variation.
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    c9812d04
sram.c 11.6 KB