• Peter Zijlstra's avatar
    perf, x86: Add PEBS infrastructure · ca037701
    Peter Zijlstra authored
    This patch implements support for Intel Precise Event Based Sampling,
    which is an alternative counter mode in which the counter triggers a
    hardware assist to collect information on events. The hardware assist
    takes a trap like snapshot of a subset of the machine registers.
    
    This data is written to the Intel Debug-Store, which can be programmed
    with a data threshold at which to raise a PMI.
    
    With the PEBS hardware assist being trap like, the reported IP is always
    one instruction after the actual instruction that triggered the event.
    
    This implements a simple PEBS model that always takes a single PEBS event
    at a time. This is done so that the interaction with the rest of the
    system is as expected (freq adjust, period randomization, lbr,
    callchains, etc.).
    
    It adds an ABI element: perf_event_attr::precise, which indicates that we
    wish to use this (constrained, but precise) mode.
    Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
    Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
    Cc: paulus@samba.org
    Cc: eranian@google.com
    Cc: robert.richter@amd.com
    Cc: fweisbec@gmail.com
    LKML-Reference: <20100304140100.392111285@chello.nl>
    Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
    ca037701
perf_event_intel.c 23.6 KB