• Lennert Buytenhek's avatar
    [ARM] 3377/2: add support for intel xsc3 core · 23bdf86a
    Lennert Buytenhek authored
    Patch from Lennert Buytenhek
    
    This patch adds support for the new XScale v3 core.  This is an
    ARMv5 ISA core with the following additions:
    
    - L2 cache
    - I/O coherency support (on select chipsets)
    - Low-Locality Reference cache attributes (replaces mini-cache)
    - Supersections (v6 compatible)
    - 36-bit addressing (v6 compatible)
    - Single instruction cache line clean/invalidate
    - LRU cache replacement (vs round-robin)
    
    I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
    cores have separate errata and have to handle things like L2, so it
    is simpler to keep it separate.
    
    L2 cache support is currently a build option because the L2 enable
    bit must be set before we enable the MMU and there is no easy way to
    capture command line parameters at this point.
    
    There are still optimizations that can be done such as using LLR for
    copypage (in theory using the exisiting mini-cache code) but those
    can be addressed down the road.
    Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
    Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    23bdf86a
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