• Stanislav Lisovskiy's avatar
    drm/i915: Adjust CDCLK accordingly to our DBuf bw needs · cd191546
    Stanislav Lisovskiy authored
    According to BSpec max BW per slice is calculated using formula
    Max BW = CDCLK * 64. Currently when calculating min CDCLK we
    account only per plane requirements, however in order to avoid
    FIFO underruns we need to estimate accumulated BW consumed by
    all planes(ddb entries basically) residing on that particular
    DBuf slice. This will allow us to put CDCLK lower and save power
    when we don't need that much bandwidth or gain additional
    performance once plane consumption grows.
    
    v2: - Fix long line warning
        - Limited new DBuf bw checks to only gens >= 11
    
    v3: - Lets track used Dbuf bw per slice and per crtc in bw state
          (or may be in DBuf state in future), that way we don't need
          to have all crtcs in state and those only if we detect if
          are actually going to change cdclk, just same way as we
          do with other stuff, i.e intel_atomic_serialize_global_state
          and co. Just as per Ville's paradigm.
        - Made dbuf bw calculation procedure look nicer by introducing
          for_each_dbuf_slice_in_mask - we often will now need to iterate
          slices using mask.
        - According to experimental results CDCLK * 64 accounts for
          overall bandwidth across all dbufs, not per dbuf.
    
    v4: - Fixed missing const(Ville)
        - Removed spurious whitespaces(Ville)
        - Fixed local variable init(reduced scope where not needed)
        - Added some comments about data rate for planar formats
        - Changed struct intel_crtc_bw to intel_dbuf_bw
        - Moved dbuf bw calculation to intel_compute_min_cdclk(Ville)
    
    v5: - Removed unneeded macro
    
    v6: - Prevent too frequent CDCLK switching back and forth:
          Always switch to higher CDCLK when needed to prevent bandwidth
          issues, however don't switch to lower CDCLK earlier than once
          in 30 minutes in order to prevent constant modeset blinking.
          We could of course not switch back at all, however this is
          bad from power consumption point of view.
    
    v7: - Fixed to track cdclk using bw_state, modeset will be now
          triggered only when CDCLK change is really needed.
    
    v8: - Lock global state if bw_state->min_cdclk is changed.
        - Try getting bw_state only if there are crtcs in the commit
          (need to have read-locked global state)
    
    v9: - Do not do Dbuf bw check for gens < 9 - triggers WARN
          as ddb_size is 0.
    
    v10: - Lock global state for older gens as well.
    
    v11: - Define new bw_calc_min_cdclk hook, instead of using
           a condition(Manasi Navare)
    
    v12: - Fixed rebase conflict
    
    v13: - Added spaces after declarations to make checkpatch happy.
    Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
    Reviewed-by: default avatarManasi Navare <manasi.d.navare@intel.com>
    Signed-off-by: default avatarManasi Navare <manasi.d.navare@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20200520150058.16123-1-stanislav.lisovskiy@intel.com
    cd191546
intel_bw.h 1.75 KB