• Andrew Morton's avatar
    [PATCH] ppc32: IBM 40x and 4xx fixes · cec6721d
    Andrew Morton authored
    From: Tom Rini <trini@kernel.crashing.org>
    
    On IBM 40x and IBM 4xx (or more specifically, all Book E processors), the
    Save/Restor Registers 2 and 3 Critical Save and Restore Registers 0 and 1
    are logically and functionally equivalent.  And since the 40x is the early
    variant on the Book E model, make generic 4xx/BookE code refer to
    CSRR0/CSRR1, and map these to SRR2/SRR3 on 40x.
    cec6721d
reg_booke.h 13.7 KB