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Florian Fainelli authored
Add a very minimalistic BCM63138 Device Tree include file which describes the BCM63138 SoC with only the basic set of required peripherals: - Cortex A9 CPUs - ARM GIC - ARM SCU - PL310 Level-2 cache controller - ARM TWD & Global timers - ARM TWD watchdog - legacy MIPS bus (UBUS) - BCM6345-style UARTs (disabled by default) Since the PL310 L2 cache controller does not come out of reset with correct default values, we need to override the 'cache-sets' and 'cache-size' properties to get its geometry right. Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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