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Rajendra Nayak authored
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR and instead attempt a CPU RET and side effect, MPU RET in suspend. NOTE: the hardware was originally designed to be capable of achieving deep power states such as OFF and OSWR, however due to various issues and risks, deepest valid state was determined to be CSWR - hence we use the errata framework to handle this case. Signed-off-by:
Rajendra Nayak <rnayak@ti.com> [nm@ti.com: updates] Signed-off-by:
Nishanth Menon <nm@ti.com> Reviewed-by:
Kevin Hilman <khilman@linaro.org> Tested-by:
Kevin Hilman <khilman@linaro.org>
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