• Nicholas Piggin's avatar
    powerpc/64s: Reduce exception alignment · f4329f2e
    Nicholas Piggin authored
    Exception handlers are aligned to 128 bytes (L1 cache) on 64s, which is
    overkill. It can reduce the icache footprint of any individual exception
    path. However taken as a whole, the expansion in icache footprint seems
    likely to be counter-productive and cause more total misses.
    
    Create IFETCH_ALIGN_SHIFT/BYTES, which should give optimal ifetch
    alignment with much more reasonable alignment. This saves 1792 bytes
    from head_64.o text with an allmodconfig build.
    
    Other subarchitectures should define appropriate IFETCH_ALIGN_SHIFT
    values if this becomes more widely used.
    Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    f4329f2e
cache.h 2.29 KB