• Vineet Gupta's avatar
    ARC: Timers/counters/delay management · d8005e6b
    Vineet Gupta authored
    ARC700 includes 2 in-core 32bit timers TIMER0 and TIMER1.
    Both have exactly same capabilies.
    
    * programmable to count from TIMER<n>_CNT to TIMER<n>_LIMIT
    * for count 0 and LIMIT ~1, provides a free-running counter by
        auto-wrapping when limit is reached.
    * optionally interrupt when LIMIT is reached (oneshot event semantics)
    * rearming the interrupt provides periodic semantics
    * run at CPU clk
    
    ARC Linux uses TIMER0 for clockevent (periodic/oneshot) and TIMER1 for
    clocksource (free-running clock).
    
    Newer cores provide RTSC insn which gives a 64bit cpu clk snapshot hence
    is more apt for clocksource when available.
    
    SMP poses a bit of challenge for global timekeeping clocksource /
    sched_clock() backend:
     -TIMER1 based local clocks are out-of-sync hence can't be used
      (thus we default to jiffies based cs as well as sched_clock() one/both
      of which platform can override with it's specific hardware assist)
     -RTSC is only allowed in SMP if it's cross-core-sync (Kconfig glue
      ensures that) and thus usable for both requirements.
    Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    d8005e6b
timex.h 508 Bytes