• David S. Miller's avatar
    [PATCH] PCI: DMA bursting advice · e24c2d96
    David S. Miller authored
    After seeing, at best, "guesses" as to the following kind
    of information in several drivers, I decided that we really
    need a way for platforms to specifically give advice in this
    area for what works best with their PCI controller implementation.
    
    Basically, this new interface gives DMA bursting advice on
    PCI.  There are three forms of the advice:
    
    1) Burst as much as possible, it is not necessary to end bursts
       on some particular boundary for best performance.
    
    2) Burst on some byte count multiple.  A DMA burst to some multiple of
       number of bytes may be done, but it is important to end the burst
       on an exact multiple for best performance.
    
       The best example of this I am aware of are the PPC64 PCI
       controllers, where if you end a burst mid-cacheline then
       chip has to refetch the data and the IOMMU translations
       which hurts performance a lot.
    
    3) Burst on a single byte count multiple.  Bursts shall end
       exactly on the next multiple boundary for best performance.
    
       Sparc64 and Alpha's PCI controllers operate this way.  They
       disconnect any device which tries to burst across a cacheline
       boundary.
    
       Actually, newer sparc64 PCI controllers do not have this behavior.
       That is why the "pdev" is passed into the interface, so I can
       add code later to check which PCI controller the system is using
       and give advice accordingly.
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
    e24c2d96
pci.h 3.34 KB