• Matt Roper's avatar
    drm/i915/rkl: Add DPLL4 support · e66f609b
    Matt Roper authored
    Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
    enable a third display.  Unlike EHL's variant of DPLL4, the RKL variant
    behaves the same as DPLL0/1.  And despite its name, the DPLL4 registers
    are offset as if it were DPLL2.
    
    v2:
     - Add new .update_ref_clks() hook.
    
    v3:
     - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas)
    
    v4:
     - Don't drop _MMIO_PLL3; although it's now unused, we're going to need
       it very soon again for upcoming DG1 patches.  (Lucas)
    
    v5:
     - Don't re-number TBT PLL and beyond, just use new RKL_DPLL_CFGCR
       macros to lookup the proper registers instead.  Although renumbering
       the PLLs might be something we want to consider down the road, it
       opens a big can of worms right now since a bunch of places in the
       code have an assumption that the PLL table has idx==id and no holes.
       Renumbering creates a hole for TGL, so we'd either need to allow
       holes in the table or break the idx==id invariant, both of which are
       somewhat invasive changes to the design.
    
    Bspec: 49202
    Bspec: 49443
    Bspec: 50288
    Bspec: 50289
    Cc: Lucas De Marchi <lucas.demarchi@intel.com>
    Cc: José Roberto de Souza <jose.souza@intel.com>
    Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20200716220551.2730644-4-matthew.d.roper@intel.comReviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
    Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    e66f609b
intel_dpll_mgr.c 124 KB