• Imre Deak's avatar
    drm/i915/icl: Reserve all required PLLs for TypeC ports · eea72c4c
    Imre Deak authored
    When enabling a TypeC port we need to reserve all the required PLLs for
    it, the TBT PLL for TBT-alt and the MG PHY PLL for DP-alt/legacy sinks.
    We can select the proper PLL for the current port mode from the reserved
    PLLs only once we selected and locked down the port mode for the whole
    duration of the port's active state. Resetting and locking down the port
    mode can in turn happen only during the modeset commit phase once we
    disabled the given port and the PLL it used.
    
    To support the above reserve-and-select PLL semantic we store the
    reserved PLLs along with their HW state in the CRTC state and provide a
    way to select the active PLL from these. The selected PLL along with its
    HW state will be pointed at by crtc_state->shared_dpll/dpll_hw_state as
    in the case of other port types.
    
    Besides reserving all required PLLs no functional changes.
    
    v2:
    - Fix releasing the ICL PLLs, not clearing the PLLs from the old
      crtc_state.
    - Init port_dpll to ICL_PORT_DPLL_DEFAULT closer to where port_dpll is
      used for symmetry with the corresponding ICL_PORT_DPLL_MG_PHY init.
      (Ville)
    v3:
    - Add FIXME: for clearing the ICL port PLLs from the new crtc state.
    
    Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
    Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190628143635.22066-20-imre.deak@intel.com
    eea72c4c
intel_dpll_mgr.h 8.93 KB