• Kumar Gala's avatar
    [PATCH] ppc32: Support 36-bit physical addressing on e500 · f50b153b
    Kumar Gala authored
    To add support for 36-bit physical addressing on e500 the following changes
    have been made.  The changes are generalized to support any physical address
    size larger than 32-bits:
    
    * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits
      of flags.
    
    * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of
      updating hardware register (SPRN_MAS7) which holds the upper 32-bits of
      physical address that will be written into the TLB.  This is useful since
      not all e500 cores support 36-bit physical addressing.
    
    * Currently have a pass through implementation of fixup_bigphys_addr
    
    * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional
      storage attributes that may exist in future FSL Book-E cores and updated
      fault handler to copy these bits into the hardware TLBs.
    Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
    Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
    Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
    f50b153b
ppc85xx_common.c 980 Bytes