• Prabhakar Kushwaha's avatar
    powerpc/mpc85xx:Add initial device tree support of T104x · fb734eee
    Prabhakar Kushwaha authored
    The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
    processor cores with high-performance data path acceleration architecture
    and network peripheral interfaces required for networking & telecommunications.
    
    T1042 personality is a reduced personality of T1040 without Integrated 8-port
    Gigabit Ethernet switch.
    
    The T1040/T1042 SoC includes the following function and features:
    
     - Four e5500 cores, each with a private 256 KB L2 cache
     - 256 KB shared L3 CoreNet platform cache (CPC)
     - Interconnect CoreNet platform
     - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
       support
     - Data Path Acceleration Architecture (DPAA) incorporating acceleration
     for the following functions:
        -  Packet parsing, classification, and distribution
        -  Queue management for scheduling, packet sequencing, and congestion
        	management
        -  Cryptography Acceleration (SEC 5.0)
        - RegEx Pattern Matching Acceleration (PME 2.2)
        - IEEE Std 1588 support
        - Hardware buffer management for buffer allocation and deallocation
     - Ethernet interfaces
        - Integrated 8-port Gigabit Ethernet switch (T1040 only)
        - Four 1 Gbps Ethernet controllers
     - Two RGMII interfaces or one RGMII and one MII interfaces
     - High speed peripheral interfaces
       - Four PCI Express 2.0 controllers running at up to 5 GHz
       - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
       - Upto two QSGMII interface
       - Upto six SGMII interface supporting 1000 Mbps
       - One SGMII interface supporting upto 2500 Mbps
     - Additional peripheral interfaces
       - Two USB 2.0 controllers with integrated PHY
       - SD/eSDHC/eMMC
       -  eSPI controller
       - Four I2C controllers
       - Four UARTs
       - Four GPIO controllers
       - Integrated flash controller (IFC)
       - Change this to  LCD/ HDMI interface (DIU) with 12 bit dual data rate
       - TDM interface
     - Multicore programmable interrupt controller (PIC)
     - Two 8-channel DMA engines
     - Single source clocking implementation
     - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
    Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
    Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
    Signed-off-by: default avatarVarun Sethi <Varun.Sethi@freescale.com>
    Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
    Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
    fb734eee
t1040si-post.dtsi 11.1 KB