• Daniel Vetter's avatar
    drm/i915: store adjusted dotclock in adjusted_mode->clock · ff9a6750
    Daniel Vetter authored
    ... not the port clock. This allows us to kill the funny semantics
    around pixel_target_clock.
    
    Since the dpll code still needs the real port clock, add a new
    port_clock field to the pipe configuration. Handling the default case
    for that one is a bit tricky, since encoders might not consistently
    overwrite it when retrying the crtc/encoder bw arbitrage step in the
    compute config stage. Hence we need to always clear port_clock and
    update it again if the encoder hasn't put in something more specific.
    This can't be done in one step since the encoder might want to adjust
    the mode first.
    
    I was a bit on the fence whether I should subsume the pixel multiplier
    handling into the port_clock, too. But then I decided against this
    since it's on an abstract level still the dotclock of the adjusted
    mode, and only our hw makes it a bit special due to the separate pixel
    mulitplier setting (which requires that the dpll runs at the
    non-multiplied dotclock).
    
    So after this patch the adjusted_mode accurately describes the mode we
    feed into the port, after the panel fitter and pixel multiplier (or
    line doubling, if we ever bother with that) have done their job.
    Since the fdi link is between the pfit and the pixel multiplier steps
    we need to be careful with calculating the fdi link config.
    
    v2: Fix up ilk cpu pll handling.
    
    v3: Introduce an fdi_dotclock variable in ironlake_fdi_compute_config
    to make it clearer that we transmit the adjusted_mode without the
    pixel multiplier taken into account. The old code multiplied the the
    available link bw with the pixel multiplier, which results in the same
    fdi configuration, but is much more confusing.
    
    v4: Rebase on top of Imre's is_cpu_edp removal.
    
    v5: Rebase on top of Paulo's haswell watermark fixes, which introduce
    a new place which looked at the pixel_clock and so needed conversion.
    
    v6: Split out prep patches as requested by Paulo Zanoni. Also rebase
    on top of the fdi dotclock handling fix in the fdi lanes/bw
    computation code.
    
    Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v3)
    Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v6)
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    ff9a6750
intel_dp.c 88.9 KB