Commit 00c674e4 authored by Thierry Reding's avatar Thierry Reding Committed by Peter De Schrijver

clk: tegra: Fix clock rate computation

The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 480fe6f4
...@@ -411,6 +411,8 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, ...@@ -411,6 +411,8 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
return -EINVAL; return -EINVAL;
} }
cfg->output_rate >>= p_div;
if (pll->params->pdiv_tohw) { if (pll->params->pdiv_tohw) {
ret = _p_div_to_hw(hw, 1 << p_div); ret = _p_div_to_hw(hw, 1 << p_div);
if (ret < 0) if (ret < 0)
......
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