drm/amd/display: Force delay after DP receive power up

[Why]
Some sprcified monitor scalar cannot recognize timing
change on demand. Once the link phy disable and enable
during a short period then the Sink protection mechanism
could keep the screen in blank and cannot be recoverred.

[How]
To add 100ms delay between enable link phy and link training.
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -1559,9 +1559,10 @@ bool perform_link_training_with_retries(
 			pipe_ctx->clock_source->id,
 			link_setting);
 
-		if (stream->sink_patches.dppowerup_delay > 0) {
-			int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
-
+		if ((link && link->dc->debug.dppowerup_delay > 0) || stream->sink_patches.dppowerup_delay > 0) {
+			int delay_dp_power_up_in_ms =
+				(link->dc->debug.dppowerup_delay >= stream->sink_patches.dppowerup_delay) ?
+				link->dc->debug.dppowerup_delay : stream->sink_patches.dppowerup_delay;
 			msleep(delay_dp_power_up_in_ms);
 		}
 

drivers/gpu/drm/amd/display/dc/dc.h

@@ -498,6 +498,7 @@ struct dc_debug_options {
 	bool usbc_combo_phy_reset_wa;
 	bool disable_dsc;
 	bool enable_dram_clock_change_one_display_vactive;
+	unsigned int dppowerup_delay;
 };
 
 struct dc_debug_data {