Commit 014fd22e authored by Xiubo Li's avatar Xiubo Li Committed by Mark Brown

ASoC: fsl-sai: Convert to use regmap framework's endianness method.

Signed-off-by: default avatarXiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent 66491507
...@@ -18,9 +18,8 @@ Required properties: ...@@ -18,9 +18,8 @@ Required properties:
- pinctrl-names: Must contain a "default" entry. - pinctrl-names: Must contain a "default" entry.
- pinctrl-NNN: One property must exist for each entry in pinctrl-names. - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
See ../pinctrl/pinctrl-bindings.txt for details of the property values. See ../pinctrl/pinctrl-bindings.txt for details of the property values.
- big-endian-regs: If this property is absent, the little endian mode will - big-endian: Boolean property, required if all the FTM_PWM registers
be in use as default, or the big endian mode will be in use for all the are big-endian rather than little-endian.
device registers.
- big-endian-data: If this property is absent, the little endian mode will - big-endian-data: If this property is absent, the little endian mode will
be in use as default, or the big endian mode will be in use for all the be in use as default, or the big endian mode will be in use for all the
fifo data. fifo data.
...@@ -38,6 +37,6 @@ sai2: sai@40031000 { ...@@ -38,6 +37,6 @@ sai2: sai@40031000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
big-endian-regs; big-endian;
big-endian-data; big-endian-data;
}; };
...@@ -539,7 +539,7 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) ...@@ -539,7 +539,7 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
} }
} }
static struct regmap_config fsl_sai_regmap_config = { static const struct regmap_config fsl_sai_regmap_config = {
.reg_bits = 32, .reg_bits = 32,
.reg_stride = 4, .reg_stride = 4,
.val_bits = 32, .val_bits = 32,
...@@ -568,10 +568,6 @@ static int fsl_sai_probe(struct platform_device *pdev) ...@@ -568,10 +568,6 @@ static int fsl_sai_probe(struct platform_device *pdev)
if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
sai->sai_on_imx = true; sai->sai_on_imx = true;
sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
if (sai->big_endian_regs)
fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
sai->big_endian_data = of_property_read_bool(np, "big-endian-data"); sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
......
...@@ -131,7 +131,6 @@ struct fsl_sai { ...@@ -131,7 +131,6 @@ struct fsl_sai {
struct clk *bus_clk; struct clk *bus_clk;
struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
bool big_endian_regs;
bool big_endian_data; bool big_endian_data;
bool is_dsp_mode; bool is_dsp_mode;
bool sai_on_imx; bool sai_on_imx;
......
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