Commit 023e76b1 authored by Vignesh R's avatar Vignesh R Committed by Greg Kroah-Hartman

iio: adc: ti_am335x_adc: Increase timeout value waiting for ADC sample

commit 7175cce1 upstream.

Now that open delay and sample delay for each channel is configurable
via DT, the default IDLE_TIMEOUT value is not enough as this is
calculated based on hardcoded macros. This results in driver returning
EBUSY sometimes. Fix this by increasing the timeout
value based on maximum value possible to open delay and sample delays
for each channel.

Fixes: 5dc11e81 ("iio: adc: ti_am335x_adc: make sample delay, open delay, averaging DT parameters")
Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
Acked-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a1f72192
......@@ -382,7 +382,7 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
timeout = jiffies + usecs_to_jiffies
timeout = jiffies + msecs_to_jiffies
(IDLE_TIMEOUT * adc_dev->channels);
/* Wait for Fifo threshold interrupt */
while (1) {
......
......@@ -138,16 +138,16 @@
/*
* time in us for processing a single channel, calculated as follows:
*
* num cycles = open delay + (sample delay + conv time) * averaging
* max num cycles = open delay + (sample delay + conv time) * averaging
*
* num cycles: 152 + (1 + 13) * 16 = 376
* max num cycles: 262143 + (255 + 13) * 16 = 266431
*
* clock frequency: 26MHz / 8 = 3.25MHz
* clock period: 1 / 3.25MHz = 308ns
*
* processing time: 376 * 308ns = 116us
* max processing time: 266431 * 308ns = 83ms(approx)
*/
#define IDLE_TIMEOUT 116 /* microsec */
#define IDLE_TIMEOUT 83 /* milliseconds */
#define TSCADC_CELLS 2
......
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