Commit 02d7cb95 authored by Caesar Wang's avatar Caesar Wang Committed by Greg Kroah-Hartman

arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

commit 78ec79bf upstream.

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarJonathan Cameron <jic23@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent bf436012
......@@ -270,6 +270,8 @@ saradc: saradc@ff100000 {
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
......
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