Commit 0399eca8 authored by Kalle Valo's avatar Kalle Valo

ath10k: cleanup ath10k_pci_wait_for_target_init()

ath10k_pci_wait_for_target_init() did really follow the style used elsewhere in
ath10k. Use ath10k_pci_read/write() wrappers, simplify the while loop and
improve warning messages.
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 36a8f413
...@@ -48,6 +48,9 @@ MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option"); ...@@ -48,6 +48,9 @@ MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
/* how long wait to wait for target to initialise, in ms */
#define ATH10K_PCI_TARGET_WAIT 3000
#define QCA988X_2_0_DEVICE_ID (0x003c) #define QCA988X_2_0_DEVICE_ID (0x003c)
static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = { static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
...@@ -2385,30 +2388,41 @@ static int ath10k_pci_deinit_irq(struct ath10k *ar) ...@@ -2385,30 +2388,41 @@ static int ath10k_pci_deinit_irq(struct ath10k *ar)
static int ath10k_pci_wait_for_target_init(struct ath10k *ar) static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
int wait_limit = 300; /* 3 sec */ unsigned long timeout;
int ret; int ret;
u32 val;
ret = ath10k_pci_wake(ar); ret = ath10k_pci_wake(ar);
if (ret) { if (ret) {
ath10k_err("failed to wake up target: %d\n", ret); ath10k_err("failed to wake up target for init: %d\n", ret);
return ret; return ret;
} }
while (wait_limit-- && timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
!(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
FW_IND_INITIALIZED)) { do {
val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
/* target should never return this */
if (val == 0xffffffff)
continue;
if (val & FW_IND_INITIALIZED)
break;
if (ar_pci->num_msi_intrs == 0) if (ar_pci->num_msi_intrs == 0)
/* Fix potential race by repeating CORE_BASE writes */ /* Fix potential race by repeating CORE_BASE writes */
iowrite32(PCIE_INTR_FIRMWARE_MASK | ath10k_pci_soc_write32(ar, PCIE_INTR_ENABLE_ADDRESS,
PCIE_INTR_CE_MASK_ALL, PCIE_INTR_FIRMWARE_MASK |
ar_pci->mem + (SOC_CORE_BASE_ADDRESS | PCIE_INTR_CE_MASK_ALL);
PCIE_INTR_ENABLE_ADDRESS));
mdelay(10); mdelay(10);
} } while (time_before(jiffies, timeout));
if (wait_limit < 0) { if (val == 0xffffffff || !(val & FW_IND_INITIALIZED)) {
ath10k_err("target stalled\n"); ath10k_err("failed to receive initialized event from target: %08x\n",
ret = -EIO; val);
ret = -ETIMEDOUT;
goto out; goto out;
} }
......
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