Commit 03a9e512 authored by Tony Lindgren's avatar Tony Lindgren

omap1: Use asm_irq_flags for entry-macro.S

Initialize asm_irq_flags in omap_init_irq and use it in
get_irqnr_and_base to detect between omap7xx and omap15xx/16xx.

Note that both INT_1510_IH2_IRQ and INT_1510_IH2_IRQ are defined
as 0, so use INT_1510_IH2_IRQ for both of them.
Tested-by: default avatarJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent cf7d7e5a
...@@ -14,18 +14,17 @@ ...@@ -14,18 +14,17 @@
#include <mach/irqs.h> #include <mach/irqs.h>
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \ /*
(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) * We use __glue to avoid errors with multiple definitions of
#error "FIXME: OMAP7XX doesn't support multiple-OMAP" * .globl omap_irq_flags as it's included from entry-armv.S but not
#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) * from entry-common.S.
#define INT_IH2_IRQ INT_7XX_IH2_IRQ */
#elif defined(CONFIG_ARCH_OMAP15XX) #ifdef __glue
#define INT_IH2_IRQ INT_1510_IH2_IRQ .pushsection .data
#elif defined(CONFIG_ARCH_OMAP16XX) .globl omap_irq_flags
#define INT_IH2_IRQ INT_1610_IH2_IRQ omap_irq_flags:
#else .word 0
#warning "IH2 IRQ defaulted" .popsection
#define INT_IH2_IRQ INT_1510_IH2_IRQ
#endif #endif
.macro disable_fiq .macro disable_fiq
...@@ -47,9 +46,11 @@ ...@@ -47,9 +46,11 @@
beq 1510f beq 1510f
ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
ldr \tmp, =omap_irq_flags @ irq flags address
ldr \tmp, [\tmp, #0] @ irq flags value
cmp \irqnr, #0 cmp \irqnr, #0
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
cmpeq \irqnr, #INT_IH2_IRQ cmpeq \irqnr, \tmp
ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
addeqs \irqnr, \irqnr, #32 addeqs \irqnr, \irqnr, #32
......
...@@ -176,26 +176,31 @@ static struct irq_chip omap_irq_chip = { ...@@ -176,26 +176,31 @@ static struct irq_chip omap_irq_chip = {
void __init omap_init_irq(void) void __init omap_init_irq(void)
{ {
extern unsigned int omap_irq_flags;
int i, j; int i, j;
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
if (cpu_is_omap7xx()) { if (cpu_is_omap7xx()) {
omap_irq_flags = INT_7XX_IH2_IRQ;
irq_banks = omap7xx_irq_banks; irq_banks = omap7xx_irq_banks;
irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
} }
#endif #endif
#ifdef CONFIG_ARCH_OMAP15XX #ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) { if (cpu_is_omap1510()) {
omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap1510_irq_banks; irq_banks = omap1510_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
} }
if (cpu_is_omap310()) { if (cpu_is_omap310()) {
omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap310_irq_banks; irq_banks = omap310_irq_banks;
irq_bank_count = ARRAY_SIZE(omap310_irq_banks); irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
} }
#endif #endif
#if defined(CONFIG_ARCH_OMAP16XX) #if defined(CONFIG_ARCH_OMAP16XX)
if (cpu_is_omap16xx()) { if (cpu_is_omap16xx()) {
omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap1610_irq_banks; irq_banks = omap1610_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
} }
......
...@@ -77,7 +77,7 @@ ...@@ -77,7 +77,7 @@
/* /*
* OMAP-1610 specific IRQ numbers for interrupt handler 1 * OMAP-1610 specific IRQ numbers for interrupt handler 1
*/ */
#define INT_1610_IH2_IRQ 0 #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
#define INT_1610_IH2_FIQ 2 #define INT_1610_IH2_FIQ 2
#define INT_1610_McBSP2_TX 4 #define INT_1610_McBSP2_TX 4
#define INT_1610_McBSP2_RX 5 #define INT_1610_McBSP2_RX 5
......
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