Commit 067e75b3 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/gmc9: set vram_width properly for SR-IOV

For SR-IOV, vram_width can't be read from ATOM as
RAVEN, and DF related registers is not readable, so hardcord
is the only way to set the correct vram_width.
Reviewed-by: default avatarYintian Tao <yttao@amd.com>
Signed-off-by: default avatarTrigger Huang <Trigger.Huang@amd.com>
Signed-off-by: default avatarYintian Tao <yttao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5887a599
...@@ -813,8 +813,16 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) ...@@ -813,8 +813,16 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
int chansize, numchan; int chansize, numchan;
int r; int r;
if (amdgpu_emu_mode != 1) if (amdgpu_sriov_vf(adev)) {
/* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
* and DF related registers is not readable, seems hardcord is the
* only way to set the correct vram_width
*/
adev->gmc.vram_width = 2048;
} else if (amdgpu_emu_mode != 1) {
adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
}
if (!adev->gmc.vram_width) { if (!adev->gmc.vram_width) {
/* hbm memory channel size */ /* hbm memory channel size */
if (adev->flags & AMD_IS_APU) if (adev->flags & AMD_IS_APU)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment