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Commit 06b7972d authored by Samuel Pitoiset's avatar Samuel Pitoiset Committed by Ben Skeggs
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drm/nouveau/pm/nv50: add compute and graphics signals/sources 

These signals and sources have been reverse engineered from NVIDIA
PerfKit (Windows) and CUPTI (Linux), they will be used to build complex
hardware events from the userspace.

This commit also adds a new class for GT200.
Signed-off-by: default avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 6137b5a7
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Inline Side-by-side
Showing with 485 additions and 11 deletions
drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
View file @ 06b7972d
......@@ -24,6 +24,7 @@ nvkm_pm(void *obj)
extern struct nvkm_oclass *nv40_pm_oclass;
extern struct nvkm_oclass *nv50_pm_oclass;
extern struct nvkm_oclass *g84_pm_oclass;
extern struct nvkm_oclass *gt200_pm_oclass;
extern struct nvkm_oclass *gt215_pm_oclass;
extern struct nvkm_oclass gf100_pm_oclass;
extern struct nvkm_oclass gk104_pm_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ 06b7972d
......@@ -288,7 +288,7 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->cname = "MCP77/MCP78";
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
View file @ 06b7972d
......@@ -2,6 +2,7 @@ nvkm-y += nvkm/engine/pm/base.o
nvkm-y += nvkm/engine/pm/nv40.o
nvkm-y += nvkm/engine/pm/nv50.o
nvkm-y += nvkm/engine/pm/g84.o
nvkm-y += nvkm/engine/pm/gt200.o
nvkm-y += nvkm/engine/pm/gt215.o
nvkm-y += nvkm/engine/pm/gf100.o
nvkm-y += nvkm/engine/pm/gk104.o
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
View file @ 06b7972d
......@@ -23,15 +23,112 @@
*/
#include "nv40.h"
const struct nvkm_specsrc
g84_vfetch_sources[] = {
{ 0x400c0c, (const struct nvkm_specmux[]) {
{ 0x3, 0, "unk0" },
{}
}, "pgraph_vfetch_unk0c" },
{}
};
static const struct nvkm_specsrc
g84_crop_sources[] = {
{ 0x407008, (const struct nvkm_specmux[]) {
{ 0xf, 0, "sel0", true },
{ 0x7, 16, "sel1", true },
{}
}, "pgraph_rop0_crop_pm_mux" },
{}
};
static const struct nvkm_specsrc
g84_tex_sources[] = {
{ 0x408808, (const struct nvkm_specmux[]) {
{ 0xfffff, 0, "unk0" },
{}
}, "pgraph_tpc0_tex_unk08" },
{}
};
static const struct nvkm_specdom
g84_pm[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{ 0xf0, (const struct nvkm_specsig[]) {
{ 0xbd, "pc01_gr_idle" },
{ 0x5e, "pc01_strmout_00" },
{ 0x5f, "pc01_strmout_01" },
{ 0xd2, "pc01_trast_00" },
{ 0xd3, "pc01_trast_01" },
{ 0xd4, "pc01_trast_02" },
{ 0xd5, "pc01_trast_03" },
{ 0xd8, "pc01_trast_04" },
{ 0xd9, "pc01_trast_05" },
{ 0x5c, "pc01_vattr_00" },
{ 0x5d, "pc01_vattr_01" },
{ 0x66, "pc01_vfetch_00", g84_vfetch_sources },
{ 0x67, "pc01_vfetch_01", g84_vfetch_sources },
{ 0x68, "pc01_vfetch_02", g84_vfetch_sources },
{ 0x69, "pc01_vfetch_03", g84_vfetch_sources },
{ 0x6a, "pc01_vfetch_04", g84_vfetch_sources },
{ 0x6b, "pc01_vfetch_05", g84_vfetch_sources },
{ 0x6c, "pc01_vfetch_06", g84_vfetch_sources },
{ 0x6d, "pc01_vfetch_07", g84_vfetch_sources },
{ 0x6e, "pc01_vfetch_08", g84_vfetch_sources },
{ 0x6f, "pc01_vfetch_09", g84_vfetch_sources },
{ 0x70, "pc01_vfetch_0a", g84_vfetch_sources },
{ 0x71, "pc01_vfetch_0b", g84_vfetch_sources },
{ 0x72, "pc01_vfetch_0c", g84_vfetch_sources },
{ 0x73, "pc01_vfetch_0d", g84_vfetch_sources },
{ 0x74, "pc01_vfetch_0e", g84_vfetch_sources },
{ 0x75, "pc01_vfetch_0f", g84_vfetch_sources },
{ 0x76, "pc01_vfetch_10", g84_vfetch_sources },
{ 0x77, "pc01_vfetch_11", g84_vfetch_sources },
{ 0x78, "pc01_vfetch_12", g84_vfetch_sources },
{ 0x79, "pc01_vfetch_13", g84_vfetch_sources },
{ 0x7a, "pc01_vfetch_14", g84_vfetch_sources },
{ 0x7b, "pc01_vfetch_15", g84_vfetch_sources },
{ 0x7c, "pc01_vfetch_16", g84_vfetch_sources },
{ 0x7d, "pc01_vfetch_17", g84_vfetch_sources },
{ 0x7e, "pc01_vfetch_18", g84_vfetch_sources },
{ 0x7f, "pc01_vfetch_19", g84_vfetch_sources },
{ 0x07, "pc01_zcull_00", nv50_zcull_sources },
{ 0x08, "pc01_zcull_01", nv50_zcull_sources },
{ 0x09, "pc01_zcull_02", nv50_zcull_sources },
{ 0x0a, "pc01_zcull_03", nv50_zcull_sources },
{ 0x0b, "pc01_zcull_04", nv50_zcull_sources },
{ 0x0c, "pc01_zcull_05", nv50_zcull_sources },
{ 0xa4, "pc01_unk00" },
{ 0xec, "pc01_trailer" },
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{ 0xa0, (const struct nvkm_specsig[]) {
{ 0x30, "pc02_crop_00", g84_crop_sources },
{ 0x31, "pc02_crop_01", g84_crop_sources },
{ 0x32, "pc02_crop_02", g84_crop_sources },
{ 0x33, "pc02_crop_03", g84_crop_sources },
{ 0x00, "pc02_prop_00", nv50_prop_sources },
{ 0x01, "pc02_prop_01", nv50_prop_sources },
{ 0x02, "pc02_prop_02", nv50_prop_sources },
{ 0x03, "pc02_prop_03", nv50_prop_sources },
{ 0x04, "pc02_prop_04", nv50_prop_sources },
{ 0x05, "pc02_prop_05", nv50_prop_sources },
{ 0x06, "pc02_prop_06", nv50_prop_sources },
{ 0x07, "pc02_prop_07", nv50_prop_sources },
{ 0x48, "pc02_tex_00", g84_tex_sources },
{ 0x49, "pc02_tex_01", g84_tex_sources },
{ 0x4a, "pc02_tex_02", g84_tex_sources },
{ 0x4b, "pc02_tex_03", g84_tex_sources },
{ 0x1a, "pc02_tex_04", g84_tex_sources },
{ 0x1b, "pc02_tex_05", g84_tex_sources },
{ 0x1c, "pc02_tex_06", g84_tex_sources },
{ 0x44, "pc02_zrop_00", nv50_zrop_sources },
{ 0x45, "pc02_zrop_01", nv50_zrop_sources },
{ 0x46, "pc02_zrop_02", nv50_zrop_sources },
{ 0x47, "pc02_zrop_03", nv50_zrop_sources },
{ 0x8c, "pc02_trailer" },
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c 0 → 100644
View file @ 06b7972d
/*
* Copyright 2015 Nouveau project
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Samuel Pitoiset
*/
#include "nv40.h"
const struct nvkm_specsrc
gt200_crop_sources[] = {
{ 0x407008, (const struct nvkm_specmux[]) {
{ 0x7, 0, "sel0", true },
{ 0x1f, 16, "sel1", true },
{}
}, "pgraph_rop0_crop_pm_mux" },
{}
};
const struct nvkm_specsrc
gt200_prop_sources[] = {
{ 0x408750, (const struct nvkm_specmux[]) {
{ 0x3f, 0, "sel", true },
{}
}, "pgraph_tpc0_prop_pm_mux" },
{}
};
const struct nvkm_specsrc
gt200_tex_sources[] = {
{ 0x408508, (const struct nvkm_specmux[]) {
{ 0x3fff, 0, "unk0" },
{}
}, "pgraph_tpc0_tex_unk08" },
{}
};
static const struct nvkm_specdom
gt200_pm[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0xf0, (const struct nvkm_specsig[]) {
{ 0xc9, "pc01_gr_idle" },
{ 0x84, "pc01_strmout_00" },
{ 0x85, "pc01_strmout_01" },
{ 0xde, "pc01_trast_00" },
{ 0xdf, "pc01_trast_01" },
{ 0xe0, "pc01_trast_02" },
{ 0xe1, "pc01_trast_03" },
{ 0xe4, "pc01_trast_04" },
{ 0xe5, "pc01_trast_05" },
{ 0x82, "pc01_vattr_00" },
{ 0x83, "pc01_vattr_01" },
{ 0x46, "pc01_vfetch_00", g84_vfetch_sources },
{ 0x47, "pc01_vfetch_01", g84_vfetch_sources },
{ 0x48, "pc01_vfetch_02", g84_vfetch_sources },
{ 0x49, "pc01_vfetch_03", g84_vfetch_sources },
{ 0x4a, "pc01_vfetch_04", g84_vfetch_sources },
{ 0x4b, "pc01_vfetch_05", g84_vfetch_sources },
{ 0x4c, "pc01_vfetch_06", g84_vfetch_sources },
{ 0x4d, "pc01_vfetch_07", g84_vfetch_sources },
{ 0x4e, "pc01_vfetch_08", g84_vfetch_sources },
{ 0x4f, "pc01_vfetch_09", g84_vfetch_sources },
{ 0x50, "pc01_vfetch_0a", g84_vfetch_sources },
{ 0x51, "pc01_vfetch_0b", g84_vfetch_sources },
{ 0x52, "pc01_vfetch_0c", g84_vfetch_sources },
{ 0x53, "pc01_vfetch_0d", g84_vfetch_sources },
{ 0x54, "pc01_vfetch_0e", g84_vfetch_sources },
{ 0x55, "pc01_vfetch_0f", g84_vfetch_sources },
{ 0x56, "pc01_vfetch_10", g84_vfetch_sources },
{ 0x57, "pc01_vfetch_11", g84_vfetch_sources },
{ 0x58, "pc01_vfetch_12", g84_vfetch_sources },
{ 0x59, "pc01_vfetch_13", g84_vfetch_sources },
{ 0x5a, "pc01_vfetch_14", g84_vfetch_sources },
{ 0x5b, "pc01_vfetch_15", g84_vfetch_sources },
{ 0x5c, "pc01_vfetch_16", g84_vfetch_sources },
{ 0x5d, "pc01_vfetch_17", g84_vfetch_sources },
{ 0x5e, "pc01_vfetch_18", g84_vfetch_sources },
{ 0x5f, "pc01_vfetch_19", g84_vfetch_sources },
{ 0x07, "pc01_zcull_00", nv50_zcull_sources },
{ 0x08, "pc01_zcull_01", nv50_zcull_sources },
{ 0x09, "pc01_zcull_02", nv50_zcull_sources },
{ 0x0a, "pc01_zcull_03", nv50_zcull_sources },
{ 0x0b, "pc01_zcull_04", nv50_zcull_sources },
{ 0x0c, "pc01_zcull_05", nv50_zcull_sources },
{ 0xb0, "pc01_unk00" },
{ 0xec, "pc01_trailer" },
{}
}, &nv40_perfctr_func },
{ 0xe0, (const struct nvkm_specsig[]) {
{ 0x55, "pc02_crop_00", gt200_crop_sources },
{ 0x56, "pc02_crop_01", gt200_crop_sources },
{ 0x57, "pc02_crop_02", gt200_crop_sources },
{ 0x58, "pc02_crop_03", gt200_crop_sources },
{ 0x00, "pc02_prop_00", gt200_prop_sources },
{ 0x01, "pc02_prop_01", gt200_prop_sources },
{ 0x02, "pc02_prop_02", gt200_prop_sources },
{ 0x03, "pc02_prop_03", gt200_prop_sources },
{ 0x04, "pc02_prop_04", gt200_prop_sources },
{ 0x05, "pc02_prop_05", gt200_prop_sources },
{ 0x06, "pc02_prop_06", gt200_prop_sources },
{ 0x07, "pc02_prop_07", gt200_prop_sources },
{ 0x78, "pc02_tex_00", gt200_tex_sources },
{ 0x79, "pc02_tex_01", gt200_tex_sources },
{ 0x7a, "pc02_tex_02", gt200_tex_sources },
{ 0x7b, "pc02_tex_03", gt200_tex_sources },
{ 0x32, "pc02_tex_04", gt200_tex_sources },
{ 0x33, "pc02_tex_05", gt200_tex_sources },
{ 0x34, "pc02_tex_06", gt200_tex_sources },
{ 0x74, "pc02_zrop_00", nv50_zrop_sources },
{ 0x75, "pc02_zrop_01", nv50_zrop_sources },
{ 0x76, "pc02_zrop_02", nv50_zrop_sources },
{ 0x77, "pc02_zrop_03", nv50_zrop_sources },
{ 0xec, "pc02_trailer" },
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nvkm_oclass *
gt200_pm_oclass = &(struct nv40_pm_oclass) {
.base.handle = NV_ENGINE(PM, 0xa0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_pm_ctor,
.dtor = _nvkm_pm_dtor,
.init = _nvkm_pm_init,
.fini = _nvkm_pm_fini,
},
.doms = gt200_pm,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
View file @ 06b7972d
......@@ -23,15 +23,95 @@
*/
#include "nv40.h"
// TODO: check for GT200
static const struct nvkm_specsrc
gt215_zcull_sources[] = {
{ 0x4002ca4, (const struct nvkm_specmux[]) {
{ 0x7fff, 0, "unk0" },
{ 0xff, 24, "unk24" },
{}
}, "pgraph_zcull_pm_unka4" },
{}
};
static const struct nvkm_specdom
gt215_pm[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{ 0xf0, (const struct nvkm_specsig[]) {
{ 0xcb, "pc01_gr_idle" },
{ 0x86, "pc01_strmout_00" },
{ 0x87, "pc01_strmout_01" },
{ 0xe0, "pc01_trast_00" },
{ 0xe1, "pc01_trast_01" },
{ 0xe2, "pc01_trast_02" },
{ 0xe3, "pc01_trast_03" },
{ 0xe6, "pc01_trast_04" },
{ 0xe7, "pc01_trast_05" },
{ 0x84, "pc01_vattr_00" },
{ 0x85, "pc01_vattr_01" },
{ 0x46, "pc01_vfetch_00", g84_vfetch_sources },
{ 0x47, "pc01_vfetch_01", g84_vfetch_sources },
{ 0x48, "pc01_vfetch_02", g84_vfetch_sources },
{ 0x49, "pc01_vfetch_03", g84_vfetch_sources },
{ 0x4a, "pc01_vfetch_04", g84_vfetch_sources },
{ 0x4b, "pc01_vfetch_05", g84_vfetch_sources },
{ 0x4c, "pc01_vfetch_06", g84_vfetch_sources },
{ 0x4d, "pc01_vfetch_07", g84_vfetch_sources },
{ 0x4e, "pc01_vfetch_08", g84_vfetch_sources },
{ 0x4f, "pc01_vfetch_09", g84_vfetch_sources },
{ 0x50, "pc01_vfetch_0a", g84_vfetch_sources },
{ 0x51, "pc01_vfetch_0b", g84_vfetch_sources },
{ 0x52, "pc01_vfetch_0c", g84_vfetch_sources },
{ 0x53, "pc01_vfetch_0d", g84_vfetch_sources },
{ 0x54, "pc01_vfetch_0e", g84_vfetch_sources },
{ 0x55, "pc01_vfetch_0f", g84_vfetch_sources },
{ 0x56, "pc01_vfetch_10", g84_vfetch_sources },
{ 0x57, "pc01_vfetch_11", g84_vfetch_sources },
{ 0x58, "pc01_vfetch_12", g84_vfetch_sources },
{ 0x59, "pc01_vfetch_13", g84_vfetch_sources },
{ 0x5a, "pc01_vfetch_14", g84_vfetch_sources },
{ 0x5b, "pc01_vfetch_15", g84_vfetch_sources },
{ 0x5c, "pc01_vfetch_16", g84_vfetch_sources },
{ 0x5d, "pc01_vfetch_17", g84_vfetch_sources },
{ 0x5e, "pc01_vfetch_18", g84_vfetch_sources },
{ 0x5f, "pc01_vfetch_19", g84_vfetch_sources },
{ 0x07, "pc01_zcull_00", gt215_zcull_sources },
{ 0x08, "pc01_zcull_01", gt215_zcull_sources },
{ 0x09, "pc01_zcull_02", gt215_zcull_sources },
{ 0x0a, "pc01_zcull_03", gt215_zcull_sources },
{ 0x0b, "pc01_zcull_04", gt215_zcull_sources },
{ 0x0c, "pc01_zcull_05", gt215_zcull_sources },
{ 0xb2, "pc01_unk00" },
{ 0xec, "pc01_trailer" },
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
{ 0xe0, (const struct nvkm_specsig[]) {
{ 0x64, "pc02_crop_00", gt200_crop_sources },
{ 0x65, "pc02_crop_01", gt200_crop_sources },
{ 0x66, "pc02_crop_02", gt200_crop_sources },
{ 0x67, "pc02_crop_03", gt200_crop_sources },
{ 0x00, "pc02_prop_00", gt200_prop_sources },
{ 0x01, "pc02_prop_01", gt200_prop_sources },
{ 0x02, "pc02_prop_02", gt200_prop_sources },
{ 0x03, "pc02_prop_03", gt200_prop_sources },
{ 0x04, "pc02_prop_04", gt200_prop_sources },
{ 0x05, "pc02_prop_05", gt200_prop_sources },
{ 0x06, "pc02_prop_06", gt200_prop_sources },
{ 0x07, "pc02_prop_07", gt200_prop_sources },
{ 0x80, "pc02_tex_00", gt200_tex_sources },
{ 0x81, "pc02_tex_01", gt200_tex_sources },
{ 0x82, "pc02_tex_02", gt200_tex_sources },
{ 0x83, "pc02_tex_03", gt200_tex_sources },
{ 0x3a, "pc02_tex_04", gt200_tex_sources },
{ 0x3b, "pc02_tex_05", gt200_tex_sources },
{ 0x3c, "pc02_tex_06", gt200_tex_sources },
{ 0x7c, "pc02_zrop_00", nv50_zrop_sources },
{ 0x7d, "pc02_zrop_01", nv50_zrop_sources },
{ 0x7e, "pc02_zrop_02", nv50_zrop_sources },
{ 0x7f, "pc02_zrop_03", nv50_zrop_sources },
{ 0xcc, "pc02_trailer" },
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nvkm_specsig[]) {
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
View file @ 06b7972d
......@@ -23,22 +23,146 @@
*/
#include "nv40.h"
const struct nvkm_specsrc
nv50_prop_sources[] = {
{ 0x408e50, (const struct nvkm_specmux[]) {
{ 0x1f, 0, "sel", true },
{}
}, "pgraph_tpc0_prop_pm_mux" },
{}
};
const struct nvkm_specsrc
nv50_zcull_sources[] = {
{ 0x4002ca4, (const struct nvkm_specmux[]) {
{ 0x7fff, 0, "unk0" },
{}
}, "pgraph_zcull_pm_unka4" },
{}
};
const struct nvkm_specsrc
nv50_zrop_sources[] = {
{ 0x40708c, (const struct nvkm_specmux[]) {
{ 0xf, 0, "sel0", true },
{ 0xf, 16, "sel1", true },
{}
}, "pgraph_rop0_zrop_pm_mux" },
{}
};
static const struct nvkm_specsrc
nv50_crop_sources[] = {
{ 0x407008, (const struct nvkm_specmux[]) {
{ 0x7, 0, "sel0", true },
{ 0x7, 16, "sel1", true },
{}
}, "pgraph_rop0_crop_pm_mux" },
{}
};
static const struct nvkm_specsrc
nv50_tex_sources[] = {
{ 0x408808, (const struct nvkm_specmux[]) {
{ 0x3fff, 0, "unk0" },
{}
}, "pgraph_tpc0_tex_unk08" },
{}
};
static const struct nvkm_specsrc
nv50_vfetch_sources[] = {
{ 0x400c0c, (const struct nvkm_specmux[]) {
{ 0x1, 0, "unk0" },
{}
}, "pgraph_vfetch_unk0c" },
{}
};
static const struct nvkm_specdom
nv50_pm[] = {
{ 0x040, (const struct nvkm_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nvkm_specsig[]) {
{ 0xc8, "gr_idle" },
{ 0xf0, (const struct nvkm_specsig[]) {
{ 0xc8, "pc01_gr_idle" },
{ 0x7f, "pc01_strmout_00" },
{ 0x80, "pc01_strmout_01" },
{ 0xdc, "pc01_trast_00" },
{ 0xdd, "pc01_trast_01" },
{ 0xde, "pc01_trast_02" },
{ 0xdf, "pc01_trast_03" },
{ 0xe2, "pc01_trast_04" },
{ 0xe3, "pc01_trast_05" },
{ 0x7c, "pc01_vattr_00" },
{ 0x7d, "pc01_vattr_01" },
{ 0x26, "pc01_vfetch_00", nv50_vfetch_sources },
{ 0x27, "pc01_vfetch_01", nv50_vfetch_sources },
{ 0x28, "pc01_vfetch_02", nv50_vfetch_sources },
{ 0x29, "pc01_vfetch_03", nv50_vfetch_sources },
{ 0x2a, "pc01_vfetch_04", nv50_vfetch_sources },
{ 0x2b, "pc01_vfetch_05", nv50_vfetch_sources },
{ 0x2c, "pc01_vfetch_06", nv50_vfetch_sources },
{ 0x2d, "pc01_vfetch_07", nv50_vfetch_sources },
{ 0x2e, "pc01_vfetch_08", nv50_vfetch_sources },
{ 0x2f, "pc01_vfetch_09", nv50_vfetch_sources },
{ 0x30, "pc01_vfetch_0a", nv50_vfetch_sources },
{ 0x31, "pc01_vfetch_0b", nv50_vfetch_sources },
{ 0x32, "pc01_vfetch_0c", nv50_vfetch_sources },
{ 0x33, "pc01_vfetch_0d", nv50_vfetch_sources },
{ 0x34, "pc01_vfetch_0e", nv50_vfetch_sources },
{ 0x35, "pc01_vfetch_0f", nv50_vfetch_sources },
{ 0x36, "pc01_vfetch_10", nv50_vfetch_sources },
{ 0x37, "pc01_vfetch_11", nv50_vfetch_sources },
{ 0x38, "pc01_vfetch_12", nv50_vfetch_sources },
{ 0x39, "pc01_vfetch_13", nv50_vfetch_sources },
{ 0x3a, "pc01_vfetch_14", nv50_vfetch_sources },
{ 0x3b, "pc01_vfetch_15", nv50_vfetch_sources },
{ 0x3c, "pc01_vfetch_16", nv50_vfetch_sources },
{ 0x3d, "pc01_vfetch_17", nv50_vfetch_sources },
{ 0x3e, "pc01_vfetch_18", nv50_vfetch_sources },
{ 0x3f, "pc01_vfetch_19", nv50_vfetch_sources },
{ 0x20, "pc01_zcull_00", nv50_zcull_sources },
{ 0x21, "pc01_zcull_01", nv50_zcull_sources },
{ 0x22, "pc01_zcull_02", nv50_zcull_sources },
{ 0x23, "pc01_zcull_03", nv50_zcull_sources },
{ 0x24, "pc01_zcull_04", nv50_zcull_sources },
{ 0x25, "pc01_zcull_05", nv50_zcull_sources },
{ 0xae, "pc01_unk00" },
{ 0xee, "pc01_trailer" },
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nvkm_specsig[]) {
{ 0xf0, (const struct nvkm_specsig[]) {
{ 0x52, "pc02_crop_00", nv50_crop_sources },
{ 0x53, "pc02_crop_01", nv50_crop_sources },
{ 0x54, "pc02_crop_02", nv50_crop_sources },
{ 0x55, "pc02_crop_03", nv50_crop_sources },
{ 0x00, "pc02_prop_00", nv50_prop_sources },
{ 0x01, "pc02_prop_01", nv50_prop_sources },
{ 0x02, "pc02_prop_02", nv50_prop_sources },
{ 0x03, "pc02_prop_03", nv50_prop_sources },
{ 0x04, "pc02_prop_04", nv50_prop_sources },
{ 0x05, "pc02_prop_05", nv50_prop_sources },
{ 0x06, "pc02_prop_06", nv50_prop_sources },
{ 0x07, "pc02_prop_07", nv50_prop_sources },
{ 0x70, "pc02_tex_00", nv50_tex_sources },
{ 0x71, "pc02_tex_01", nv50_tex_sources },
{ 0x72, "pc02_tex_02", nv50_tex_sources },
{ 0x73, "pc02_tex_03", nv50_tex_sources },
{ 0x40, "pc02_tex_04", nv50_tex_sources },
{ 0x41, "pc02_tex_05", nv50_tex_sources },
{ 0x42, "pc02_tex_06", nv50_tex_sources },
{ 0x6c, "pc02_zrop_00", nv50_zrop_sources },
{ 0x6d, "pc02_zrop_01", nv50_zrop_sources },
{ 0x6e, "pc02_zrop_02", nv50_zrop_sources },
{ 0x6f, "pc02_zrop_03", nv50_zrop_sources },
{ 0xee, "pc02_trailer" },
{}
}, &nv40_perfctr_func },
{ 0x020, (const struct nvkm_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x040, (const struct nvkm_specsig[]) {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
View file @ 06b7972d
......@@ -44,6 +44,14 @@ struct nvkm_perfsrc {
bool enable;
};
extern const struct nvkm_specsrc nv50_prop_sources[];
extern const struct nvkm_specsrc nv50_zcull_sources[];
extern const struct nvkm_specsrc nv50_zrop_sources[];
extern const struct nvkm_specsrc g84_vfetch_sources[];
extern const struct nvkm_specsrc gt200_crop_sources[];
extern const struct nvkm_specsrc gt200_prop_sources[];
extern const struct nvkm_specsrc gt200_tex_sources[];
struct nvkm_specsig {
u8 signal;
const char *name;
......
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