[PPC32] Update CPM2 (MPC82xx/MPC85xx) code to use rheap for DP memory

Originally from: Rune Torgersen <runet@innovsys.com>
Signed-off-by: Tom Rini <trini@kernel.crashing.org>

arch/ppc/8260_io/enet.c

@@ -613,6 +613,7 @@ static int __init scc_enet_init(void)
 	struct net_device *dev;
 	struct scc_enet_private *cep;
 	int i, j, err;
+	void * dpaddr;
 	unsigned char	*eap;
 	unsigned long	mem_addr;
 	bd_t		*bd;
@@ -680,13 +681,13 @@ static int __init scc_enet_init(void)
 	 * These are relative offsets in the DP ram address space.
 	 * Initialize base addresses for the buffer descriptors.
 	 */
-	i = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
-	ep->sen_genscc.scc_rbase = i;
-	cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
+	dpaddr = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
+	ep->sen_genscc.scc_rbase = cpm2_dpram_offset(dpaddr);
+	cep->rx_bd_base = (cbd_t *)dpaddr;
 
-	i = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
-	ep->sen_genscc.scc_tbase = i;
-	cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
+	dpaddr = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
+	ep->sen_genscc.scc_tbase = cpm2_dpram_offset(dpaddr);
+	cep->tx_bd_base = (cbd_t *)dpaddr;
 
 	cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
 	cep->cur_rx = cep->rx_bd_base;

arch/ppc/8260_io/fcc_enet.c

@@ -1621,28 +1621,15 @@ init_fcc_param(fcc_info_t *fip, struct net_device *dev,
 	 */
 	memset((char *)ep, 0, sizeof(fcc_enet_t));
 
-	/* Allocate space for the buffer descriptors in the DP ram.
-	 * These are relative offsets in the DP ram address space.
+	/* Allocate space for the buffer descriptors from regular memory.
 	 * Initialize base addresses for the buffer descriptors.
 	 */
-#if 0
-	/* I really want to do this, but for some reason it doesn't
-	 * work with the data cache enabled, so I allocate from the
-	 * main memory instead.
-	 */
-	i = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
-	ep->fen_genfcc.fcc_rbase = (uint)&immap->im_dprambase[i];
-	cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
-
-	i = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
-	ep->fen_genfcc.fcc_tbase = (uint)&immap->im_dprambase[i];
-	cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
-#else
-	cep->rx_bd_base = (cbd_t *)cpm2_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
+	cep->rx_bd_base = (cbd_t *)kmalloc(sizeof(cbd_t) * RX_RING_SIZE,
+			GFP_KERNEL | GFP_DMA);
 	ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
-	cep->tx_bd_base = (cbd_t *)cpm2_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
+	cep->tx_bd_base = (cbd_t *)kmalloc(sizeof(cbd_t) * TX_RING_SIZE,
+			GFP_KERNEL | GFP_DMA);
 	ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
-#endif
 
 	cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
 	cep->cur_rx = cep->rx_bd_base;

arch/ppc/lib/Makefile

@@ -6,3 +6,4 @@ obj-y			:= checksum.o string.o strcase.o dec_and_lock.o div64.o
 
 obj-$(CONFIG_SMP)	+= locks.o
 obj-$(CONFIG_8xx)	+= rheap.o
+obj-$(CONFIG_CPM2)	+= rheap.o

arch/ppc/syslib/cpm2_common.c

@@ -22,17 +22,16 @@
 #include <linux/mm.h>
 #include <linux/interrupt.h>
 #include <linux/bootmem.h>
+#include <linux/module.h>
 #include <asm/irq.h>
 #include <asm/mpc8260.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/immap_cpm2.h>
 #include <asm/cpm2.h>
+#include <asm/rheap.h>
 
-static	uint	dp_alloc_base;	/* Starting offset in DP ram */
-static	uint	dp_alloc_top;	/* Max offset + 1 */
-static	uint	host_buffer;	/* One page of host buffer */
-static	uint	host_end;	/* end + 1 */
+static void cpm2_dpinit(void);
 cpm_cpm2_t	*cpmp;		/* Pointer to comm processor space */
 
 /* We allocate this here because it is used almost exclusively for
@@ -43,83 +42,17 @@ cpm2_map_t *cpm2_immr;
 void
 cpm2_reset(void)
 {
-	uint vpgaddr;
-
 	cpm2_immr = (cpm2_map_t *)CPM_MAP_ADDR;
 
 	/* Reclaim the DP memory for our use.
-	*/
-	dp_alloc_base = CPM_DATAONLY_BASE;
-	dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE;
-
-	/* Set the host page for allocation.
-	*/
-	host_buffer =
-		(uint) alloc_bootmem_pages(PAGE_SIZE * NUM_CPM_HOST_PAGES);
-	host_end = host_buffer + (PAGE_SIZE * NUM_CPM_HOST_PAGES);
-
-	vpgaddr = host_buffer;
+	 */
+	cpm2_dpinit();
 
 	/* Tell everyone where the comm processor resides.
-	*/
+	 */
 	cpmp = &cpm2_immr->im_cpm;
 }
 
-/* Allocate some memory from the dual ported ram.
- * To help protocols with object alignment restrictions, we do that
- * if they ask.
- */
-uint
-cpm2_dpalloc(uint size, uint align)
-{
-	uint	retloc;
-	uint	align_mask, off;
-	uint	savebase;
-
-	align_mask = align - 1;
-	savebase = dp_alloc_base;
-
-	if ((off = (dp_alloc_base & align_mask)) != 0)
-		dp_alloc_base += (align - off);
-
-	if ((dp_alloc_base + size) >= dp_alloc_top) {
-		dp_alloc_base = savebase;
-		return(CPM_DP_NOSPACE);
-	}
-
-	retloc = dp_alloc_base;
-	dp_alloc_base += size;
-
-	return(retloc);
-}
-
-/* We also own one page of host buffer space for the allocation of
- * UART "fifos" and the like.
- */
-uint
-cpm2_hostalloc(uint size, uint align)
-{
-	uint	retloc;
-	uint	align_mask, off;
-	uint	savebase;
-
-	align_mask = align - 1;
-	savebase = host_buffer;
-
-	if ((off = (host_buffer & align_mask)) != 0)
-		host_buffer += (align - off);
-
-	if ((host_buffer + size) >= host_end) {
-		host_buffer = savebase;
-		return(0);
-	}
-
-	retloc = host_buffer;
-	host_buffer += size;
-
-	return(retloc);
-}
-
 /* Set a baud rate generator.  This needs lots of work.  There are
  * eight BRGs, which can be connected to the CPM channels or output
  * as clocks.  The BRGs are in two different block of internal
@@ -174,3 +107,99 @@ cpm2_fastbrg(uint brg, uint rate, int div16)
 	if (div16)
 		*bp |= CPM_BRG_DIV16;
 }
+
+/*
+ * dpalloc / dpfree bits.
+ */
+static spinlock_t cpm_dpmem_lock;
+/* 16 blocks should be enough to satisfy all requests
+ * until the memory subsystem goes up... */
+static rh_block_t cpm_boot_dpmem_rh_block[16];
+static rh_info_t cpm_dpmem_info;
+
+static void cpm2_dpinit(void)
+{
+	void *dprambase = &((cpm2_map_t *)CPM_MAP_ADDR)->im_dprambase;
+
+	spin_lock_init(&cpm_dpmem_lock);
+
+	/* initialize the info header */
+	rh_init(&cpm_dpmem_info, 1,
+			sizeof(cpm_boot_dpmem_rh_block) /
+			sizeof(cpm_boot_dpmem_rh_block[0]),
+			cpm_boot_dpmem_rh_block);
+
+	/* Attach the usable dpmem area */
+	/* XXX: This is actually crap. CPM_DATAONLY_BASE and
+	 * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
+	 * varies with the processor and the microcode patches activated.
+	 * But the following should be at least safe.
+	 */
+	rh_attach_region(&cpm_dpmem_info, dprambase + CPM_DATAONLY_BASE,
+			CPM_DATAONLY_SIZE);
+}
+
+/* This function used to return an index into the DPRAM area.
+ * Now it returns the actuall physical address of that area.
+ * use cpm2_dpram_offset() to get the index
+ */
+void *cpm2_dpalloc(uint size, uint align)
+{
+	void *start;
+	unsigned long flags;
+
+	spin_lock_irqsave(&cpm_dpmem_lock, flags);
+	cpm_dpmem_info.alignment = align;
+	start = rh_alloc(&cpm_dpmem_info, size, "commproc");
+	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
+
+	return start;
+}
+EXPORT_SYMBOL(cpm2_dpalloc);
+
+int cpm2_dpfree(void *addr)
+{
+	int ret;
+	unsigned long flags;
+
+	spin_lock_irqsave(&cpm_dpmem_lock, flags);
+	ret = rh_free(&cpm_dpmem_info, addr);
+	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL(cpm2_dpfree);
+
+/* not sure if this is ever needed */
+void *cpm2_dpalloc_fixed(void *addr, uint size, uint align)
+{
+	void *start;
+	unsigned long flags;
+
+	spin_lock_irqsave(&cpm_dpmem_lock, flags);
+	cpm_dpmem_info.alignment = align;
+	start = rh_alloc_fixed(&cpm_dpmem_info, addr, size, "commproc");
+	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
+
+	return start;
+}
+EXPORT_SYMBOL(cpm2_dpalloc_fixed);
+
+void cpm2_dpdump(void)
+{
+	rh_dump(&cpm_dpmem_info);
+}
+EXPORT_SYMBOL(cpm2_dpdump);
+
+uint cpm2_dpram_offset(void *addr)
+{
+	return (uint)((u_char *)addr -
+			((uint)((cpm2_map_t *)CPM_MAP_ADDR)->im_dprambase));
+}
+EXPORT_SYMBOL(cpm2_dpram_offset);
+
+void *cpm2_dpram_addr(int offset)
+{
+	return (void *)&((cpm2_map_t *)CPM_MAP_ADDR)->im_dprambase[offset];
+}
+EXPORT_SYMBOL(cpm2_dpram_addr);

drivers/serial/cpm_uart/cpm_uart_cpm2.c

@@ -181,6 +181,7 @@ void scc4_lineif(struct uart_cpm_port *pinfo)
 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 {
 	int dpmemsz, memsz;
+	u8 *dp_mem;
 	uint dp_addr;
 	u8 *mem_addr;
 	dma_addr_t dma_addr = 0;
@@ -188,13 +189,15 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 	pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
 
 	dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
-	dp_addr = cpm2_dpalloc(dpmemsz, 8);
-	if (dp_addr == CPM_DP_NOSPACE) {
+	dp_mem = cpm2_dpalloc(dpmemsz, 8);
+	if (dp_mem == NULL) {
 		printk(KERN_ERR
 		       "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
 		return -ENOMEM;
 	}
 
+	dp_addr = cpm2_dpram_offset(dp_mem);
+
 	memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
 	    L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
 	if (is_con)
@@ -203,10 +206,8 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 		mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
 					      GFP_KERNEL);
 
-	/* We cant really from memory allocated via cpm2_dpalloc,
-	 * fix this if in the future we can */
 	if (mem_addr == NULL) {
-		/* XXX cpm_dpalloc does not yet free */
+		cpm2_dpfree(dp_mem);
 		printk(KERN_ERR
 		       "cpm_uart_cpm1.c: could not allocate coherent memory\n");
 		return -ENOMEM;
@@ -220,7 +221,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 	pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
 						       * pinfo->rx_fifosize);
 
-	pinfo->rx_bd_base = (volatile cbd_t *)(DPRAM_BASE + dp_addr);
+	pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
 	pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
 
 	return 0;
@@ -234,7 +235,7 @@ void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
 					 pinfo->tx_fifosize), pinfo->mem_addr,
 			  pinfo->dma_addr);
 
-	/* XXX cannot free dpmem yet */
+	cpm2_dpfree(&pinfo->dp_addr);
 }
 
 /* Setup any dynamic params in the uart desc */

include/asm-ppc/cpm2.h

@@ -104,10 +104,14 @@
  * and dual port ram.
  */
 extern		cpm_cpm2_t	*cpmp;	 /* Pointer to comm processor */
-uint		cpm2_dpalloc(uint size, uint align);
-uint		cpm2_hostalloc(uint size, uint align);
-void		cpm2_setbrg(uint brg, uint rate);
-void		cpm2_fastbrg(uint brg, uint rate, int div16);
+extern void *cpm2_dpalloc(uint size, uint align);
+extern int cpm2_dpfree(void *addr);
+extern void *cpm2_dpalloc_fixed(void *addr, uint size, uint allign);
+extern void cpm2_dpdump(void);
+extern unsigned int cpm2_dpram_offset(void *addr);
+extern void *cpm2_dpram_addr(int offset);
+extern void cpm2_setbrg(uint brg, uint rate);
+extern void cpm2_fastbrg(uint brg, uint rate, int div16);
 
 /* Buffer descriptors used by many of the CPM protocols.
 */