Commit 098f5305 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Simon Horman

ARM: dts: r8a779x: Add '#reset-cells' in cpg-mssr

With the latest dtc, we get many warnings about the missing
'#reset-cells' property in these controllers, e.g.:

arch/arm/boot/dts/r8a7790-lager.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /can@e6e80000:resets[0])
arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/dma-controller@e6700000:resets[0])
arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/ethernet@e6800000:resets[0])
arch/arm/boot/dts/r8a7793-gose.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /gpio@e6050000:resets[0])
arch/arm/boot/dts/r8a7794-alt.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /i2c@e6500000:resets[0])
arch/arm/boot/dts/r8a7794-silk.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /interrupt-controller@e61c0000:resets[0])

This adds it for the three r8a779x chips that were lacking it. The
binding mandates this as <1>, so this is the value I use.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
[geert: Add fix for r8a7793.dtsi]
Fixes: 34fbd2b1 ("ARM: dts: r8a7790: Add reset control properties")
Fixes: 6e11a322 ("ARM: dts: r8a7792: Add reset control properties")
Fixes: 84fb19e1 ("ARM: dts: r8a7793: Add reset control properties")
Fixes: 615beb75 ("ARM: dts: r8a7794: Add reset control properties")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent b6d3b649
...@@ -1201,6 +1201,7 @@ cpg: clock-controller@e6150000 { ...@@ -1201,6 +1201,7 @@ cpg: clock-controller@e6150000 {
clock-names = "extal", "usb_extal"; clock-names = "extal", "usb_extal";
#clock-cells = <2>; #clock-cells = <2>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
#reset-cells = <1>;
}; };
prr: chipid@ff000044 { prr: chipid@ff000044 {
......
...@@ -829,6 +829,7 @@ cpg: clock-controller@e6150000 { ...@@ -829,6 +829,7 @@ cpg: clock-controller@e6150000 {
clock-names = "extal"; clock-names = "extal";
#clock-cells = <2>; #clock-cells = <2>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
#reset-cells = <1>;
}; };
}; };
......
...@@ -1088,6 +1088,7 @@ cpg: clock-controller@e6150000 { ...@@ -1088,6 +1088,7 @@ cpg: clock-controller@e6150000 {
clock-names = "extal", "usb_extal"; clock-names = "extal", "usb_extal";
#clock-cells = <2>; #clock-cells = <2>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
#reset-cells = <1>;
}; };
rst: reset-controller@e6160000 { rst: reset-controller@e6160000 {
......
...@@ -1099,6 +1099,7 @@ cpg: clock-controller@e6150000 { ...@@ -1099,6 +1099,7 @@ cpg: clock-controller@e6150000 {
clock-names = "extal", "usb_extal"; clock-names = "extal", "usb_extal";
#clock-cells = <2>; #clock-cells = <2>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
#reset-cells = <1>;
}; };
rst: reset-controller@e6160000 { rst: reset-controller@e6160000 {
......
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