Commit 0b3534be authored by Olof Johansson's avatar Olof Johansson

Merge tag 'imx-soc-3.16' of...

Merge tag 'imx-soc-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Merge "ARM: imx: soc changes for 3.16" from Shawn Guo:

i.MX SoC changes for 3.16:
 - A few cleanups on mx21ads board file, which should make the later
   conversion to DT a little bit easier.
 - Add some missing clocks and drop unused clk lookups for i.MX1 and
   i.MX27 clock drivers
 - Add initial i.MX SoloX (imx6sx) SoC support
 - Remove mx51_babbage and mach-cpuimx51sd board files, as the
   equivalent DT support is ready for the boards
 - Clean up device tree timer initialization a little bit
 - Add missing i2c4 clock for i.MX6 DualLite/Solo
 - Add missing CKO clock i.MX25
 - Add shared gate clock support for i.MX specific clk_gate2
 - Add low-level debug support for SoC VF610
 - Some random code cleanups and defconfig updates

* tag 'imx-soc-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits)
  ARM: mx25: Add CLKO support
  ARM: i.MX1 clk: Remove clk_register_clkdev() for unused clocks
  ARM: i.MX1 clk: Add missing clocks
  ARM: imx: add basic imx6sx SoC support
  ARM: imx: add clock driver for imx6sx
  ARM: imx: add low-level debug support for imx6sx
  ARM: mx51: Remove mach-cpuimx51sd board file
  ARM: i.MX: Setup IRQ handler from IRQ driver
  ARM: i.MX27 pca100: remove deprecated IRQF_DISABLED
  ARM: imx/mxs defconfigs: add MTD_SPI_NOR (new dependency for M25P80)
  ARM: i.MX: Fix eMMa PrP resource size
  ARM: imx_v4_v5_defconfig: drop CONFIG_COMMON_CLK_DEBUG option
  ARM: i.MX27 clk: Remove clk_register_clkdev() for unused clocks
  ARM: i.MX27 clk: Add missing clocks for MSHC and RTIC
  ARM: imx6q: add the missing esai_ahb clock
  ARM: imx: add shared gate clock support
  ARM: imx: lock is always valid for clk_gate2
  ARM: imx: define struct clk_gate2 on our own
  ARM: i.MX: Remove #ifdef CONFIG_OF
  ARM: imx_v6_v7_defconfig: enable option CONFIG_LOCALVERSION_AUTO
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 16ae66cc 46ae4249
......@@ -139,6 +139,9 @@ clocks and IDs.
uart5_ipg 124
reserved 125
wdt_ipg 126
cko_div 127
cko_sel 128
cko 129
Examples:
......
......@@ -98,7 +98,12 @@ clocks and IDs.
fpm 83
mpll_osc_sel 84
mpll_sel 85
spll_gate 86
spll_gate 86
mshc_div 87
rtic_ipg_gate 88
mshc_ipg_gate 89
rtic_ahb_gate 90
mshc_baud_gate 91
Examples:
......
......@@ -220,6 +220,7 @@ clocks and IDs.
lvds2_sel 205
lvds1_gate 206
lvds2_gate 207
esai_ahb 208
Examples:
......
* Clock bindings for Freescale i.MX6 SoloX
Required properties:
- compatible: Should be "fsl,imx6sx-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
for the full list of i.MX6 SoloX clock IDs.
......@@ -317,6 +317,13 @@ choice
Say Y here if you want kernel low-level debugging support
on i.MX6SL.
config DEBUG_IMX6SX_UART
bool "i.MX6SX Debug UART"
depends on SOC_IMX6SX
help
Say Y here if you want kernel low-level debugging support
on i.MX6SX.
config DEBUG_KEYSTONE_UART0
bool "Kernel low-level debugging on KEYSTONE2 using UART0"
depends on ARCH_KEYSTONE
......@@ -935,13 +942,23 @@ config DEBUG_IMX_UART_PORT
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART || \
DEBUG_IMX6Q_UART || \
DEBUG_IMX6SL_UART
DEBUG_IMX6SL_UART || \
DEBUG_IMX6SX_UART
default 1
depends on ARCH_MXC
help
Choose UART port on which kernel low-level debug messages
should be output.
config DEBUG_VF_UART_PORT
int "Vybrid Debug UART Port Selection" if DEBUG_VF_UART
default 1
range 0 3
depends on SOC_VF610
help
Choose UART port on which kernel low-level debug messages
should be output.
config DEBUG_TEGRA_UART
bool
depends on ARCH_TEGRA
......@@ -970,7 +987,8 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART ||\
DEBUG_IMX6Q_UART || \
DEBUG_IMX6SL_UART
DEBUG_IMX6SL_UART || \
DEBUG_IMX6SX_UART
default "debug/msm.S" if DEBUG_MSM_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
......
......@@ -80,6 +80,7 @@ CONFIG_MTD_UBI=y
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_ATA=y
CONFIG_BLK_DEV_SD=y
CONFIG_PATA_IMX=y
CONFIG_NETDEVICES=y
CONFIG_CS89x0=y
......@@ -153,8 +154,12 @@ CONFIG_USB_HID=m
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
......@@ -177,7 +182,6 @@ CONFIG_RTC_DRV_MXC=y
CONFIG_DMADEVICES=y
CONFIG_IMX_SDMA=y
CONFIG_IMX_DMA=y
CONFIG_COMMON_CLK_DEBUG=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
......
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
......@@ -33,7 +32,6 @@ CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_VPR200=y
CONFIG_MACH_IMX51_DT=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
......@@ -46,7 +44,11 @@ CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CMA=y
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_ARM_IMX6Q_CPUFREQ=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_BINFMT_MISC=m
......@@ -72,6 +74,7 @@ CONFIG_RFKILL_INPUT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
CONFIG_DMA_CMA=y
CONFIG_IMX_WEIM=y
CONFIG_CONNECTOR=y
CONFIG_MTD=y
......@@ -89,6 +92,7 @@ CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
......@@ -183,6 +187,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CODA=y
CONFIG_SOC_CAMERA_OV2640=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y
......@@ -215,7 +220,6 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
......@@ -245,7 +249,7 @@ CONFIG_DRM_IMX_TVE=y
CONFIG_DRM_IMX_LDB=y
CONFIG_DRM_IMX_IPUV3_CORE=y
CONFIG_DRM_IMX_IPUV3=y
CONFIG_COMMON_CLK_DEBUG=y
CONFIG_DRM_IMX_HDMI=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PWM=y
CONFIG_PWM_IMX=y
......
......@@ -26,7 +26,6 @@ CONFIG_ARCH_MXS=y
# CONFIG_ARM_THUMB is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
......@@ -51,10 +50,10 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_M25P80=y
# CONFIG_M25PXX_USE_FAST_READ is not set
CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
# CONFIG_BLK_DEV is not set
CONFIG_EEPROM_AT24=y
......@@ -120,7 +119,6 @@ CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_UNSAFE_RESUME=y
CONFIG_MMC_MXS=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
......@@ -138,7 +136,6 @@ CONFIG_DMADEVICES=y
CONFIG_MXS_DMA=y
CONFIG_STAGING=y
CONFIG_MXS_LRADC=y
CONFIG_COMMON_CLK_DEBUG=y
CONFIG_IIO=y
CONFIG_IIO_SYSFS_TRIGGER=y
CONFIG_PWM=y
......@@ -180,7 +177,7 @@ CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_STRICT_DEVMEM=y
CONFIG_DEBUG_USER=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRYPTO_DEV_MXS_DCP=y
CONFIG_CRC_ITU_T=m
CONFIG_CRC7=m
CONFIG_FONTS=y
......@@ -81,6 +81,15 @@
#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
#define IMX6SX_UART1_BASE_ADDR 0x02020000
#define IMX6SX_UART2_BASE_ADDR 0x021e8000
#define IMX6SX_UART3_BASE_ADDR 0x021ec000
#define IMX6SX_UART4_BASE_ADDR 0x021f0000
#define IMX6SX_UART5_BASE_ADDR 0x021f4000
#define IMX6SX_UART6_BASE_ADDR 0x022a0000
#define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR
#define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n)
#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
#ifdef CONFIG_DEBUG_IMX1_UART
......@@ -103,6 +112,8 @@
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
#elif defined(CONFIG_DEBUG_IMX6SL_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
#elif defined(CONFIG_DEBUG_IMX6SX_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX)
#endif
#endif /* __DEBUG_IMX_UART_H */
......@@ -7,9 +7,20 @@
*
*/
#define VF_UART0_BASE_ADDR 0x40027000
#define VF_UART1_BASE_ADDR 0x40028000
#define VF_UART2_BASE_ADDR 0x40029000
#define VF_UART3_BASE_ADDR 0x4002a000
#define VF_UART_BASE_ADDR(n) VF_UART##n##_BASE_ADDR
#define VF_UART_BASE(n) VF_UART_BASE_ADDR(n)
#define VF_UART_PHYSICAL_BASE VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT)
#define VF_UART_VIRTUAL_BASE 0xfe000000
.macro addruart, rp, rv, tmp
ldr \rp, =0x40028000 @ physical
ldr \rv, =0xfe028000 @ virtual
ldr \rp, =VF_UART_PHYSICAL_BASE @ physical
and \rv, \rp, #0xffffff @ offset within 16MB section
add \rv, \rv, #VF_UART_VIRTUAL_BASE
.endm
.macro senduart, rd, rx
......
......@@ -702,61 +702,6 @@ endif
if ARCH_MULTI_V7
comment "i.MX51 machines:"
config MACH_IMX51_DT
bool "Support i.MX51 platforms from device tree"
select SOC_IMX51
help
Include support for Freescale i.MX51 based platforms
using the device tree for discovery
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select SOC_IMX51
help
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its
peripherals.
config MACH_EUKREA_CPUIMX51SD
bool "Support Eukrea CPUIMX51SD module"
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select SOC_IMX51
help
Include support for Eukrea CPUIMX51SD platform. This includes
specific configurations for the module and its peripherals.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX51SD
default MACH_EUKREA_MBIMXSD51_BASEBOARD
config MACH_EUKREA_MBIMXSD51_BASEBOARD
prompt "Eukrea MBIMXSD development board"
bool
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
comment "Device tree only"
config SOC_IMX50
......@@ -768,6 +713,12 @@ config SOC_IMX50
help
This enables support for Freescale i.MX50 processor.
config MACH_IMX51_DT
bool "i.MX51 support"
select SOC_IMX51
help
This enables support for Freescale i.MX51 processor
config SOC_IMX53
bool "i.MX53 support"
select HAVE_IMX_SRC
......@@ -812,6 +763,14 @@ config SOC_IMX6SL
help
This enables support for Freescale i.MX6 SoloLite processor.
config SOC_IMX6SX
bool "i.MX6 SoloX support"
select PINCTRL_IMX6SX
select SOC_IMX6
help
This enables support for Freescale i.MX6 SoloX processor.
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC
......
......@@ -101,6 +101,7 @@ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
......@@ -108,11 +109,6 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
# i.MX5 based machines
obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
......
......@@ -135,7 +135,7 @@ static __init void avic_init_gc(int idx, unsigned int irq_start)
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
}
asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
{
u32 nivector;
......@@ -190,6 +190,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
for (i = 0; i < 8; i++)
__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
set_handle_irq(avic_handle_irq);
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ(FIQ_START);
......
......@@ -27,48 +27,61 @@
* parent - fixed parent. No clk_set_parent support
*/
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
struct clk_gate2 {
struct clk_hw hw;
void __iomem *reg;
u8 bit_idx;
u8 flags;
spinlock_t *lock;
unsigned int *share_count;
};
#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
static int clk_gate2_enable(struct clk_hw *hw)
{
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate2 *gate = to_clk_gate2(hw);
u32 reg;
unsigned long flags = 0;
if (gate->lock)
spin_lock_irqsave(gate->lock, flags);
spin_lock_irqsave(gate->lock, flags);
if (gate->share_count && (*gate->share_count)++ > 0)
goto out;
reg = readl(gate->reg);
reg |= 3 << gate->bit_idx;
writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
out:
spin_unlock_irqrestore(gate->lock, flags);
return 0;
}
static void clk_gate2_disable(struct clk_hw *hw)
{
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate2 *gate = to_clk_gate2(hw);
u32 reg;
unsigned long flags = 0;
if (gate->lock)
spin_lock_irqsave(gate->lock, flags);
spin_lock_irqsave(gate->lock, flags);
if (gate->share_count && --(*gate->share_count) > 0)
goto out;
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
out:
spin_unlock_irqrestore(gate->lock, flags);
}
static int clk_gate2_is_enabled(struct clk_hw *hw)
{
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate2 *gate = to_clk_gate2(hw);
reg = readl(gate->reg);
......@@ -87,21 +100,23 @@ static struct clk_ops clk_gate2_ops = {
struct clk *clk_register_gate2(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate2_flags, spinlock_t *lock)
u8 clk_gate2_flags, spinlock_t *lock,
unsigned int *share_count)
{
struct clk_gate *gate;
struct clk_gate2 *gate;
struct clk *clk;
struct clk_init_data init;
gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
/* struct clk_gate assignments */
/* struct clk_gate2 assignments */
gate->reg = reg;
gate->bit_idx = bit_idx;
gate->flags = clk_gate2_flags;
gate->lock = lock;
gate->share_count = share_count;
init.name = name;
init.ops = &clk_gate2_ops;
......
......@@ -40,12 +40,14 @@
#define SCM_GCCR IO_ADDR_SCM(0xc)
static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
"fclk", };
static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
"prem", "fclk", };
enum imx1_clks {
dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu,
fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
mma_gate, usbd_gate, clk_max
dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
usbd_gate, clk_max
};
static struct clk *clk[clk_max];
......@@ -62,17 +64,22 @@ int __init mx1_clocks_init(unsigned long fref)
clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
ARRAY_SIZE(prem_sel_clks));
clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
ARRAY_SIZE(clko_sel_clks));
clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
......@@ -84,9 +91,6 @@ int __init mx1_clocks_init(unsigned long fref)
clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
clk_register_clkdev(clk[mma_gate], "mma", NULL);
clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
......@@ -94,20 +98,15 @@ int __init mx1_clocks_init(unsigned long fref)
clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
clk_register_clkdev(clk[hclk], "mshc", NULL);
clk_register_clkdev(clk[per3], "ssi", NULL);
clk_register_clkdev(clk[clk32], NULL, "imx1-rtc.0");
clk_register_clkdev(clk[clko], "clko", NULL);
mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
......
......@@ -62,6 +62,10 @@ static struct clk_onecell_data clk_data;
static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
static const char *per_sel_clks[] = { "ahb", "upll", };
static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
"ipg", "dummy", "dummy", "dummy",
"dummy", "dummy", "per0", "per2",
"per13", "per14", "usbotg_ahb", "dummy",};
enum mx25_clks {
dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
......@@ -82,7 +86,7 @@ enum mx25_clks {
pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
wdt_ipg, clk_max
wdt_ipg, cko_div, cko_sel, cko, clk_max
};
static struct clk *clk[clk_max];
......@@ -117,6 +121,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
clk[cko_div] = imx_clk_divider("cko_div", "cko_sel", ccm(CCM_MCR), 24, 6);
clk[cko_sel] = imx_clk_mux("cko_sel", ccm(CCM_MCR), 20, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks));
clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR), 30);
clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
......@@ -230,6 +237,12 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
/*
* Let's initially set up CLKO parent as ipg, since this configuration
* is used on some imx25 board designs to clock the audio codec.
*/
clk_set_parent(clk[cko_sel], clk[ipg]);
return 0;
}
......@@ -304,8 +317,6 @@ int __init mx25_clocks_init(void)
int __init mx25_clocks_init_dt(void)
{
struct device_node *np;
void __iomem *base;
int irq;
unsigned long osc_rate = 24000000;
/* retrieve the freqency of fixed clocks from device tree */
......@@ -325,12 +336,7 @@ int __init mx25_clocks_init_dt(void)
__mx25_clocks_init(osc_rate);
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(base, irq);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
return 0;
}
......@@ -82,7 +82,8 @@ enum mx27_clks {
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
mpll_sel, spll_gate, clk_max
mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
rtic_ahb_gate, mshc_baud_gate, clk_max
};
static struct clk *clk[clk_max];
......@@ -117,6 +118,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
}
clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
......@@ -145,9 +147,11 @@ int __init mx27_clocks_init(unsigned long fref)
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
......@@ -166,6 +170,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
......@@ -177,6 +182,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
......@@ -221,16 +227,6 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
......@@ -278,14 +274,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
......@@ -296,7 +285,6 @@ int __init mx27_clocks_init(unsigned long fref)
return 0;
}
#ifdef CONFIG_OF
int __init mx27_clocks_init_dt(void)
{
struct device_node *np;
......@@ -312,4 +300,3 @@ int __init mx27_clocks_init_dt(void)
return mx27_clocks_init(fref);
}
#endif
......@@ -191,7 +191,6 @@ int __init mx31_clocks_init(unsigned long fref)
return 0;
}
#ifdef CONFIG_OF
int __init mx31_clocks_init_dt(void)
{
struct device_node *np;
......@@ -207,4 +206,3 @@ int __init mx31_clocks_init_dt(void)
return mx31_clocks_init(fref);
}
#endif
......@@ -322,9 +322,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
static void __init mx50_clocks_init(struct device_node *np)
{
void __iomem *base;
unsigned long r;
int i, irq;
int i;
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
......@@ -372,11 +371,7 @@ static void __init mx50_clocks_init(struct device_node *np)
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(base, irq);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
}
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
......@@ -436,7 +431,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
......@@ -492,9 +486,8 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
static void __init mx53_clocks_init(struct device_node *np)
{
int i, irq;
int i;
unsigned long r;
void __iomem *base;
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
......@@ -561,7 +554,6 @@ static void __init mx53_clocks_init(struct device_node *np)
mx5_clocks_common_init(0, 0, 0, 0);
clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
......@@ -592,10 +584,6 @@ static void __init mx53_clocks_init(struct device_node *np)
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(base, irq);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
}
CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
......@@ -107,7 +107,7 @@ enum mx6q_clks {
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
};
static struct clk *clk[clk_max];
......@@ -140,11 +140,13 @@ static struct clk_div_table video_div_table[] = {
{ /* sentinel */ }
};
static unsigned int share_count_esai;
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *base;
int i, irq;
int i;
int ret;
clk[dummy] = imx_clk_fixed("dummy", 0);
......@@ -352,9 +354,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
if (cpu_is_imx6dl())
/* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
else
clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
if (cpu_is_imx6dl())
......@@ -489,10 +496,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(base, irq);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
}
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
......@@ -169,7 +169,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *base;
int irq;
int i;
int ret;
......@@ -385,9 +384,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
imx6q_set_lpm(WAIT_CLOCKED);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(base, irq);
mxc_timer_init_dt(np);
}
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
This diff is collapsed.
......@@ -28,7 +28,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
struct clk *clk_register_gate2(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
u8 clk_gate_flags, spinlock_t *lock,
unsigned int *share_count);
struct clk * imx_obtain_fixed_clock(
const char *name, unsigned long rate);
......@@ -37,7 +38,15 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
shift, 0, &imx_ccm_lock);
shift, 0, &imx_ccm_lock, NULL);
}
static inline struct clk *imx_clk_gate2_shared(const char *name,
const char *parent, void __iomem *reg, u8 shift,
unsigned int *share_count)
{
return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
shift, 0, &imx_ccm_lock, share_count);
}
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
......
......@@ -17,6 +17,7 @@ struct irq_data;
struct platform_device;
struct pt_regs;
struct clk;
struct device_node;
enum mxc_cpu_pwr_mode;
void mx1_map_io(void);
......@@ -56,6 +57,7 @@ void imx51_init_late(void);
void imx53_init_late(void);
void epit_timer_init(void __iomem *base, int irq);
void mxc_timer_init(void __iomem *, int);
void mxc_timer_init_dt(struct device_node *);
int mx1_clocks_init(unsigned long fref);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx25_clocks_init(void);
......@@ -99,19 +101,6 @@ enum mx3_cpu_pwr_mode {
void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
void imx_print_silicon_rev(const char *cpu, int srev);
void avic_handle_irq(struct pt_regs *);
void tzic_handle_irq(struct pt_regs *);
#define imx1_handle_irq avic_handle_irq
#define imx21_handle_irq avic_handle_irq
#define imx25_handle_irq avic_handle_irq
#define imx27_handle_irq avic_handle_irq
#define imx31_handle_irq avic_handle_irq
#define imx35_handle_irq avic_handle_irq
#define imx50_handle_irq tzic_handle_irq
#define imx51_handle_irq tzic_handle_irq
#define imx53_handle_irq tzic_handle_irq
void imx_enable_cpu(int cpu, bool enable);
void imx_set_cpu_jump(int cpu, void *jump_addr);
u32 imx_get_cpu_arg(int cpu);
......
......@@ -111,6 +111,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX6DL:
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
soc_id = "i.MX6Q";
break;
......
......@@ -12,7 +12,7 @@
#define imx_mx2_emmaprp_data_entry_single(soc) \
{ \
.iobase = soc ## _EMMAPRP_BASE_ADDR, \
.iosize = SZ_32, \
.iosize = SZ_256, \
.irq = soc ## _INT_EMMAPRP, \
}
......
/*
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
*
* Based on pcm970-baseboard.c which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <video/platform_lcd.h>
#include <linux/backlight.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices-imx51.h"
#include "hardware.h"
#include "iomux-mx51.h"
static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
/* LED */
MX51_PAD_NANDF_D10__GPIO3_30,
/* SWITCH */
NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
MX51_PAD_UART2_TXD__UART2_TXD,
/* UART 3 */
MX51_PAD_UART3_RXD__UART3_RXD,
MX51_PAD_UART3_TXD__UART3_TXD,
MX51_PAD_KEY_COL4__UART3_RTS,
MX51_PAD_KEY_COL5__UART3_CTS,
/* SD */
MX51_PAD_SD1_CMD__SD1_CMD,
MX51_PAD_SD1_CLK__SD1_CLK,
MX51_PAD_SD1_DATA0__SD1_DATA0,
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
/* SD1 CD */
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
/* SSI */
MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
MX51_PAD_AUD3_BB_CK__AUD3_TXC,
MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
/* LCD Backlight */
MX51_PAD_DI1_D1_CS__GPIO3_4,
/* LCD RST */
MX51_PAD_CSI1_D9__GPIO3_13,
};
#define GPIO_LED1 IMX_GPIO_NR(3, 30)
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
#define GPIO_LCDRST IMX_GPIO_NR(3, 13)
#define GPIO_LCDBL IMX_GPIO_NR(3, 4)
static void eukrea_mbimxsd51_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power)
gpio_direction_output(GPIO_LCDRST, 1);
else
gpio_direction_output(GPIO_LCDRST, 0);
}
static struct plat_lcd_data eukrea_mbimxsd51_lcd_power_data = {
.set_power = eukrea_mbimxsd51_lcd_power_set,
};
static struct platform_device eukrea_mbimxsd51_lcd_powerdev = {
.name = "platform-lcd",
.dev.platform_data = &eukrea_mbimxsd51_lcd_power_data,
};
static void eukrea_mbimxsd51_bl_set_intensity(int intensity)
{
if (intensity)
gpio_direction_output(GPIO_LCDBL, 1);
else
gpio_direction_output(GPIO_LCDBL, 0);
}
static struct generic_bl_info eukrea_mbimxsd51_bl_info = {
.name = "eukrea_mbimxsd51-bl",
.max_intensity = 0xff,
.default_intensity = 0xff,
.set_bl_intensity = eukrea_mbimxsd51_bl_set_intensity,
};
static struct platform_device eukrea_mbimxsd51_bl_dev = {
.name = "generic-bl",
.id = 1,
.dev = {
.platform_data = &eukrea_mbimxsd51_bl_info,
},
};
static const struct gpio_led eukrea_mbimxsd51_leds[] __initconst = {
{
.name = "led1",
.default_trigger = "heartbeat",
.active_low = 1,
.gpio = GPIO_LED1,
},
};
static const struct gpio_led_platform_data
eukrea_mbimxsd51_led_info __initconst = {
.leds = eukrea_mbimxsd51_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimxsd51_leds),
};
static struct gpio_keys_button eukrea_mbimxsd51_gpio_buttons[] = {
{
.gpio = GPIO_SWITCH1,
.code = BTN_0,
.desc = "BP1",
.active_low = 1,
.wakeup = 1,
},
};
static const struct gpio_keys_platform_data
eukrea_mbimxsd51_button_data __initconst = {
.buttons = eukrea_mbimxsd51_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd51_gpio_buttons),
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct i2c_board_info eukrea_mbimxsd51_i2c_devices[] = {
{
I2C_BOARD_INFO("tlv320aic23", 0x1a),
},
};
static const
struct imx_ssi_platform_data eukrea_mbimxsd51_ssi_pdata __initconst = {
.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
};
static int screen_type;
static int __init eukrea_mbimxsd51_screen_type(char *options)
{
if (!strcmp(options, "dvi"))
screen_type = 1;
else if (!strcmp(options, "tft"))
screen_type = 0;
return 0;
}
__setup("screen_type=", eukrea_mbimxsd51_screen_type);
/*
* system init for baseboard usage. Will be called by cpuimx51sd init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimxsd51_baseboard_init(void)
{
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd51_pads,
ARRAY_SIZE(eukrea_mbimxsd51_pads)))
printk(KERN_ERR "error setting mbimxsd pads !\n");
imx51_add_imx_uart(1, NULL);
imx51_add_imx_uart(2, &uart_pdata);
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_imx_ssi(0, &eukrea_mbimxsd51_ssi_pdata);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
gpio_free(GPIO_LED1);
gpio_request(GPIO_SWITCH1, "SWITCH1");
gpio_direction_input(GPIO_SWITCH1);
gpio_free(GPIO_SWITCH1);
gpio_request(GPIO_LCDRST, "LCDRST");
gpio_direction_output(GPIO_LCDRST, 0);
gpio_request(GPIO_LCDBL, "LCDBL");
gpio_direction_output(GPIO_LCDBL, 0);
if (!screen_type) {
platform_device_register(&eukrea_mbimxsd51_bl_dev);
platform_device_register(&eukrea_mbimxsd51_lcd_powerdev);
} else {
gpio_free(GPIO_LCDRST);
gpio_free(GPIO_LCDBL);
}
i2c_register_board_info(0, eukrea_mbimxsd51_i2c_devices,
ARRAY_SIZE(eukrea_mbimxsd51_i2c_devices));
gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info);
imx_add_gpio_keys(&eukrea_mbimxsd51_button_data);
imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
}
......@@ -38,7 +38,6 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
.map_io = mx25_map_io,
.init_early = imx25_init_early,
.init_irq = mx25_init_irq,
.handle_irq = imx25_handle_irq,
.init_time = imx25_timer_init,
.init_machine = imx25_dt_init,
.dt_compat = imx25_dt_board_compat,
......
......@@ -43,7 +43,6 @@ DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = imx27_timer_init,
.init_machine = imx27_dt_init,
.dt_compat = imx27_dt_board_compat,
......
......@@ -39,7 +39,6 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = imx31_dt_timer_init,
.init_machine = imx31_dt_init,
.dt_compat = imx31_dt_board_compat,
......
......@@ -43,7 +43,6 @@ DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = imx35_irq_init,
.handle_irq = imx35_handle_irq,
.init_machine = imx35_dt_init,
.dt_compat = imx35_dt_board_compat,
.restart = mxc_restart,
......
......@@ -38,7 +38,6 @@ DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
.map_io = mx51_map_io,
.init_early = imx51_init_early,
.init_irq = mx51_init_irq,
.handle_irq = imx51_handle_irq,
.init_machine = imx51_dt_init,
.init_late = imx51_init_late,
.dt_compat = imx51_dt_board_compat,
......
......@@ -142,7 +142,6 @@ MACHINE_START(APF9328, "Armadeus APF9328")
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.handle_irq = imx1_handle_irq,
.init_time = apf9328_timer_init,
.init_machine = apf9328_init,
.restart = mxc_restart,
......
......@@ -562,7 +562,6 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = armadillo5x0_timer_init,
.init_machine = armadillo5x0_init,
.restart = mxc_restart,
......
......@@ -57,7 +57,6 @@ MACHINE_START(BUG, "BugLabs BUGBase")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = bug_timer_init,
.init_machine = bug_board_init,
.restart = mxc_restart,
......
......@@ -314,7 +314,6 @@ MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = eukrea_cpuimx27_timer_init,
.init_machine = eukrea_cpuimx27_init,
.restart = mxc_restart,
......
......@@ -199,7 +199,6 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = mx35_init_irq,
.handle_irq = imx35_handle_irq,
.init_time = eukrea_cpuimx35_timer_init,
.init_machine = eukrea_cpuimx35_init,
.restart = mxc_restart,
......
This diff is collapsed.
......@@ -165,7 +165,6 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
.map_io = mx25_map_io,
.init_early = imx25_init_early,
.init_irq = mx25_init_irq,
.handle_irq = imx25_handle_irq,
.init_time = eukrea_cpuimx25_timer_init,
.init_machine = eukrea_cpuimx25_init,
.restart = mxc_restart,
......
......@@ -604,7 +604,6 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = visstrim_m10_timer_init,
.init_machine = visstrim_m10_board_init,
.restart = mxc_restart,
......
......@@ -71,7 +71,6 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = mx27ipcam_timer_init,
.init_machine = mx27ipcam_init,
.restart = mxc_restart,
......
......@@ -77,7 +77,6 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = mx27lite_timer_init,
.init_machine = mx27lite_init,
.restart = mxc_restart,
......
......@@ -31,7 +31,6 @@ static const char *imx50_dt_board_compat[] __initconst = {
DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
.map_io = mx53_map_io,
.init_irq = mx53_init_irq,
.handle_irq = imx50_handle_irq,
.init_machine = imx50_dt_init,
.dt_compat = imx50_dt_board_compat,
.restart = mxc_restart,
......
......@@ -40,7 +40,6 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.handle_irq = imx53_handle_irq,
.init_machine = imx53_dt_init,
.init_late = imx53_init_late,
.dt_compat = imx53_dt_board_compat,
......
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
static void __init imx6sx_init_machine(void)
{
struct device *parent;
mxc_arch_reset_init_dt();
parent = imx_soc_device_init();
if (parent == NULL)
pr_warn("failed to initialize soc device\n");
of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
imx_anatop_init();
}
static void __init imx6sx_init_irq(void)
{
imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
irqchip_init();
}
static const char *imx6sx_dt_compat[] __initconst = {
"fsl,imx6sx",
NULL,
};
DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
.map_io = debug_ll_io_init,
.init_irq = imx6sx_init_irq,
.init_machine = imx6sx_init_machine,
.dt_compat = imx6sx_dt_compat,
.restart = mxc_restart,
MACHINE_END
......@@ -289,7 +289,6 @@ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
.map_io = kzm_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = kzm_timer_init,
.init_machine = kzm_board_init,
.restart = mxc_restart,
......
......@@ -138,7 +138,6 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.handle_irq = imx1_handle_irq,
.init_time = mx1ads_timer_init,
.init_machine = mx1ads_init,
.restart = mxc_restart,
......@@ -149,7 +148,6 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.handle_irq = imx1_handle_irq,
.init_time = mx1ads_timer_init,
.init_machine = mx1ads_init,
.restart = mxc_restart,
......
......@@ -17,51 +17,46 @@
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/basic_mmio_gpio.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices-imx21.h"
#include "hardware.h"
#include "iomux-mx21.h"
/*
* Memory-mapped I/O on MX21ADS base board
*/
#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
#define MX21ADS_MMIO_SIZE 0xc00000
#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
(MX21ADS_MMIO_BASE_ADDR + (offset))
#define MX21ADS_CS8900A_REG (MX21_CS1_BASE_ADDR + 0x000000)
#define MX21ADS_ST16C255_IOBASE_REG (MX21_CS1_BASE_ADDR + 0x200000)
#define MX21ADS_VERSION_REG (MX21_CS1_BASE_ADDR + 0x400000)
#define MX21ADS_IO_REG (MX21_CS1_BASE_ADDR + 0x800000)
#define MX21ADS_CS8900A_MMIO_SIZE 0x200000
#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11)
#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
#define MX21ADS_MMC_CD IMX_GPIO_NR(4, 25)
#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11)
#define MX21ADS_MMGPIO_BASE (6 * 32)
/* MX21ADS_IO_REG bit definitions */
#define MX21ADS_IO_SD_WP 0x0001 /* read */
#define MX21ADS_IO_TP6 0x0001 /* write */
#define MX21ADS_IO_SW_SEL 0x0002 /* read */
#define MX21ADS_IO_TP7 0x0002 /* write */
#define MX21ADS_IO_RESET_E_UART 0x0004
#define MX21ADS_IO_RESET_BASE 0x0008
#define MX21ADS_IO_CSI_CTL2 0x0010
#define MX21ADS_IO_CSI_CTL1 0x0020
#define MX21ADS_IO_CSI_CTL0 0x0040
#define MX21ADS_IO_UART1_EN 0x0080
#define MX21ADS_IO_UART4_EN 0x0100
#define MX21ADS_IO_LCDON 0x0200
#define MX21ADS_IO_IRDA_EN 0x0400
#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
#define MX21ADS_IO_IRDA_MD0_B 0x1000
#define MX21ADS_IO_IRDA_MD1 0x2000
#define MX21ADS_IO_LED4_ON 0x4000
#define MX21ADS_IO_LED3_ON 0x8000
#define MX21ADS_IO_SD_WP (MX21ADS_MMGPIO_BASE + 0)
#define MX21ADS_IO_TP6 (MX21ADS_IO_SD_WP)
#define MX21ADS_IO_SW_SEL (MX21ADS_MMGPIO_BASE + 1)
#define MX21ADS_IO_TP7 (MX21ADS_IO_SW_SEL)
#define MX21ADS_IO_RESET_E_UART (MX21ADS_MMGPIO_BASE + 2)
#define MX21ADS_IO_RESET_BASE (MX21ADS_MMGPIO_BASE + 3)
#define MX21ADS_IO_CSI_CTL2 (MX21ADS_MMGPIO_BASE + 4)
#define MX21ADS_IO_CSI_CTL1 (MX21ADS_MMGPIO_BASE + 5)
#define MX21ADS_IO_CSI_CTL0 (MX21ADS_MMGPIO_BASE + 6)
#define MX21ADS_IO_UART1_EN (MX21ADS_MMGPIO_BASE + 7)
#define MX21ADS_IO_UART4_EN (MX21ADS_MMGPIO_BASE + 8)
#define MX21ADS_IO_LCDON (MX21ADS_MMGPIO_BASE + 9)
#define MX21ADS_IO_IRDA_EN (MX21ADS_MMGPIO_BASE + 10)
#define MX21ADS_IO_IRDA_FIR_SEL (MX21ADS_MMGPIO_BASE + 11)
#define MX21ADS_IO_IRDA_MD0_B (MX21ADS_MMGPIO_BASE + 12)
#define MX21ADS_IO_IRDA_MD1 (MX21ADS_MMGPIO_BASE + 13)
#define MX21ADS_IO_LED4_ON (MX21ADS_MMGPIO_BASE + 14)
#define MX21ADS_IO_LED3_ON (MX21ADS_MMGPIO_BASE + 15)
static const int mx21ads_pins[] __initconst = {
......@@ -143,11 +138,8 @@ static struct physmap_flash_data mx21ads_flash_data = {
.width = 4,
};
static struct resource mx21ads_flash_resource = {
.start = MX21_CS0_BASE_ADDR,
.end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
.flags = IORESOURCE_MEM,
};
static struct resource mx21ads_flash_resource =
DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M);
static struct platform_device mx21ads_nor_mtd_device = {
.name = "physmap-flash",
......@@ -160,7 +152,7 @@ static struct platform_device mx21ads_nor_mtd_device = {
};
static struct resource mx21ads_cs8900_resources[] __initdata = {
DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K),
/* irq number is run-time assigned */
DEFINE_RES_IRQ(-1),
};
......@@ -179,24 +171,50 @@ static const struct imxuart_platform_data uart_pdata_rts __initconst = {
static const struct imxuart_platform_data uart_pdata_norts __initconst = {
};
static int mx21ads_fb_init(struct platform_device *pdev)
{
u16 tmp;
static struct resource mx21ads_mmgpio_resource =
DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat");
tmp = __raw_readw(MX21ADS_IO_REG);
tmp |= MX21ADS_IO_LCDON;
__raw_writew(tmp, MX21ADS_IO_REG);
return 0;
}
static struct bgpio_pdata mx21ads_mmgpio_pdata = {
.base = MX21ADS_MMGPIO_BASE,
.ngpio = 16,
};
static void mx21ads_fb_exit(struct platform_device *pdev)
{
u16 tmp;
static struct platform_device mx21ads_mmgpio = {
.name = "basic-mmio-gpio",
.id = PLATFORM_DEVID_AUTO,
.resource = &mx21ads_mmgpio_resource,
.num_resources = 1,
.dev = {
.platform_data = &mx21ads_mmgpio_pdata,
},
};
tmp = __raw_readw(MX21ADS_IO_REG);
tmp &= ~MX21ADS_IO_LCDON;
__raw_writew(tmp, MX21ADS_IO_REG);
}
static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer =
REGULATOR_SUPPLY("lcd", "imx-fb.0");
static struct regulator_init_data mx21ads_lcd_regulator_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = &mx21ads_lcd_regulator_consumer,
.num_consumer_supplies = 1,
};
static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = {
.supply_name = "LCD",
.microvolts = 3300000,
.gpio = MX21ADS_IO_LCDON,
.enable_high = 1,
.init_data = &mx21ads_lcd_regulator_init_data,
};
static struct platform_device mx21ads_lcd_regulator = {
.name = "reg-fixed-voltage",
.id = PLATFORM_DEVID_AUTO,
.dev = {
.platform_data = &mx21ads_lcd_regulator_pdata,
},
};
/*
* Connected is a portrait Sharp-QVGA display
......@@ -229,26 +247,30 @@ static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
.pwmr = 0x00a903ff,
.lscr1 = 0x00120300,
.dmacr = 0x00020008,
.init = mx21ads_fb_init,
.exit = mx21ads_fb_exit,
};
static int mx21ads_sdhc_get_ro(struct device *dev)
{
return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
return gpio_get_value(MX21ADS_IO_SD_WP);
}
static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
int ret;
ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro");
if (ret)
return ret;
return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
}
static void mx21ads_sdhc_exit(struct device *dev, void *data)
{
free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data);
free_irq(gpio_to_irq(MX21ADS_MMC_CD), data);
gpio_free(MX21ADS_IO_SD_WP);
}
static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
......@@ -264,29 +286,9 @@ mx21ads_nand_board_info __initconst = {
.hw_ecc = 1,
};
static struct map_desc mx21ads_io_desc[] __initdata = {
/*
* Memory-mapped I/O on MX21ADS Base board:
* - CS8900A Ethernet controller
* - ST16C2552CJ UART
* - CPU and Base board version
* - Base board I/O register
*/
{
.virtual = MX21ADS_MMIO_BASE_ADDR,
.pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
.length = MX21ADS_MMIO_SIZE,
.type = MT_DEVICE,
},
};
static void __init mx21ads_map_io(void)
{
mx21_map_io();
iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
}
static struct platform_device *platform_devices[] __initdata = {
&mx21ads_mmgpio,
&mx21ads_lcd_regulator,
&mx21ads_nor_mtd_device,
};
......@@ -300,12 +302,13 @@ static void __init mx21ads_board_init(void)
imx21_add_imx_uart0(&uart_pdata_rts);
imx21_add_imx_uart2(&uart_pdata_norts);
imx21_add_imx_uart3(&uart_pdata_rts);
imx21_add_imx_fb(&mx21ads_fb_data);
imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
imx21_add_mxc_nand(&mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx21_add_imx_fb(&mx21ads_fb_data);
mx21ads_cs8900_resources[1].start =
gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
mx21ads_cs8900_resources[1].end =
......@@ -321,10 +324,9 @@ static void __init mx21ads_timer_init(void)
MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
/* maintainer: Freescale Semiconductor, Inc. */
.atag_offset = 0x100,
.map_io = mx21ads_map_io,
.map_io = mx21_map_io,
.init_early = imx21_init_early,
.init_irq = mx21_init_irq,
.handle_irq = imx21_handle_irq,
.init_time = mx21ads_timer_init,
.init_machine = mx21ads_board_init,
.restart = mxc_restart,
......
......@@ -263,7 +263,6 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
.map_io = mx25_map_io,
.init_early = imx25_init_early,
.init_irq = mx25_init_irq,
.handle_irq = imx25_handle_irq,
.init_time = mx25pdk_timer_init,
.init_machine = mx25pdk_init,
.restart = mxc_restart,
......
......@@ -544,7 +544,6 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = mx27pdk_timer_init,
.init_machine = mx27pdk_init,
.restart = mxc_restart,
......
......@@ -391,7 +391,6 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
.map_io = mx27ads_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = mx27ads_timer_init,
.init_machine = mx27ads_board_init,
.restart = mxc_restart,
......
......@@ -775,7 +775,6 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = mx31_3ds_timer_init,
.init_machine = mx31_3ds_init,
.reserve = mx31_3ds_reserve,
......
......@@ -582,7 +582,6 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
.map_io = mx31ads_map_io,
.init_early = imx31_init_early,
.init_irq = mx31ads_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = mx31ads_timer_init,
.init_machine = mx31ads_init,
.restart = mxc_restart,
......
......@@ -308,7 +308,6 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = mx31lilly_timer_init,
.init_machine = mx31lilly_board_init,
.restart = mxc_restart,
......
......@@ -291,7 +291,6 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
.map_io = mx31lite_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = mx31lite_timer_init,
.init_machine = mx31lite_init,
.restart = mxc_restart,
......
......@@ -600,7 +600,6 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = mx31moboard_timer_init,
.init_machine = mx31moboard_init,
.restart = mxc_restart,
......
......@@ -615,7 +615,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = mx35_init_irq,
.handle_irq = imx35_handle_irq,
.init_time = mx35pdk_timer_init,
.init_machine = mx35_3ds_init,
.reserve = mx35_3ds_reserve,
......
This diff is collapsed.
......@@ -267,7 +267,6 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = mxt_td60_timer_init,
.init_machine = mxt_td60_board_init,
.restart = mxc_restart,
......
......@@ -245,8 +245,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
int ret;
ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"imx-mmc-detect", data);
IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
if (ret)
printk(KERN_ERR
"pca100: Failed to request irq for sd/mmc detection\n");
......@@ -421,7 +420,6 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_machine = pca100_init,
.init_time = pca100_timer_init,
.restart = mxc_restart,
......
......@@ -703,7 +703,6 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = pcm037_timer_init,
.init_machine = pcm037_init,
.init_late = pcm037_init_late,
......
......@@ -351,7 +351,6 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.handle_irq = imx27_handle_irq,
.init_time = pcm038_timer_init,
.init_machine = pcm038_init,
.restart = mxc_restart,
......
......@@ -400,7 +400,6 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = mx35_init_irq,
.handle_irq = imx35_handle_irq,
.init_time = pcm043_timer_init,
.init_machine = pcm043_init,
.restart = mxc_restart,
......
......@@ -266,7 +266,6 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.handle_irq = imx31_handle_irq,
.init_time = qong_timer_init,
.init_machine = qong_init,
.restart = mxc_restart,
......
......@@ -137,7 +137,6 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.handle_irq = imx1_handle_irq,
.init_time = scb9328_timer_init,
.init_machine = scb9328_init,
.restart = mxc_restart,
......
......@@ -310,7 +310,6 @@ MACHINE_START(VPR200, "VPR200")
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = mx35_init_irq,
.handle_irq = imx35_handle_irq,
.init_time = vpr200_timer_init,
.init_machine = vpr200_board_init,
.restart = mxc_restart,
......
......@@ -36,6 +36,7 @@
#define MXC_CPU_MX53 53
#define MXC_CPU_IMX6SL 0x60
#define MXC_CPU_IMX6DL 0x61
#define MXC_CPU_IMX6SX 0x62
#define MXC_CPU_IMX6Q 0x63
#define IMX_CHIP_REVISION_1_0 0x10
......@@ -163,6 +164,11 @@ static inline bool cpu_is_imx6dl(void)
return __mxc_cpu_type == MXC_CPU_IMX6DL;
}
static inline bool cpu_is_imx6sx(void)
{
return __mxc_cpu_type == MXC_CPU_IMX6SX;
}
static inline bool cpu_is_imx6q(void)
{
return __mxc_cpu_type == MXC_CPU_IMX6Q;
......
......@@ -28,6 +28,9 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/mach/time.h>
......@@ -328,3 +331,15 @@ void __init mxc_timer_init(void __iomem *base, int irq)
/* Make irqs happen */
setup_irq(irq, &mxc_timer_irq);
}
void __init mxc_timer_init_dt(struct device_node *np)
{
void __iomem *base;
int irq;
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(base, irq);
}
......@@ -125,7 +125,7 @@ static __init void tzic_init_gc(int idx, unsigned int irq_start)
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
}
asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
{
u32 stat;
int i, irqofs, handled;
......@@ -189,6 +189,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
for (i = 0; i < 4; i++, irq_base += 32)
tzic_init_gc(i, irq_base);
set_handle_irq(tzic_handle_irq);
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ(FIQ_START);
......
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
#define __DT_BINDINGS_CLOCK_IMX6SX_H
#define IMX6SX_CLK_DUMMY 0
#define IMX6SX_CLK_CKIL 1
#define IMX6SX_CLK_CKIH 2
#define IMX6SX_CLK_OSC 3
#define IMX6SX_CLK_PLL1_SYS 4
#define IMX6SX_CLK_PLL2_BUS 5
#define IMX6SX_CLK_PLL3_USB_OTG 6
#define IMX6SX_CLK_PLL4_AUDIO 7
#define IMX6SX_CLK_PLL5_VIDEO 8
#define IMX6SX_CLK_PLL6_ENET 9
#define IMX6SX_CLK_PLL7_USB_HOST 10
#define IMX6SX_CLK_USBPHY1 11
#define IMX6SX_CLK_USBPHY2 12
#define IMX6SX_CLK_USBPHY1_GATE 13
#define IMX6SX_CLK_USBPHY2_GATE 14
#define IMX6SX_CLK_PCIE_REF 15
#define IMX6SX_CLK_PCIE_REF_125M 16
#define IMX6SX_CLK_ENET_REF 17
#define IMX6SX_CLK_PLL2_PFD0 18
#define IMX6SX_CLK_PLL2_PFD1 19
#define IMX6SX_CLK_PLL2_PFD2 20
#define IMX6SX_CLK_PLL2_PFD3 21
#define IMX6SX_CLK_PLL3_PFD0 22
#define IMX6SX_CLK_PLL3_PFD1 23
#define IMX6SX_CLK_PLL3_PFD2 24
#define IMX6SX_CLK_PLL3_PFD3 25
#define IMX6SX_CLK_PLL2_198M 26
#define IMX6SX_CLK_PLL3_120M 27
#define IMX6SX_CLK_PLL3_80M 28
#define IMX6SX_CLK_PLL3_60M 29
#define IMX6SX_CLK_TWD 30
#define IMX6SX_CLK_PLL4_POST_DIV 31
#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
#define IMX6SX_CLK_PLL5_POST_DIV 33
#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
#define IMX6SX_CLK_STEP 35
#define IMX6SX_CLK_PLL1_SW 36
#define IMX6SX_CLK_OCRAM_SEL 37
#define IMX6SX_CLK_PERIPH_PRE 38
#define IMX6SX_CLK_PERIPH2_PRE 39
#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
#define IMX6SX_CLK_PCIE_AXI_SEL 42
#define IMX6SX_CLK_GPU_AXI_SEL 43
#define IMX6SX_CLK_GPU_CORE_SEL 44
#define IMX6SX_CLK_EIM_SLOW_SEL 45
#define IMX6SX_CLK_USDHC1_SEL 46
#define IMX6SX_CLK_USDHC2_SEL 47
#define IMX6SX_CLK_USDHC3_SEL 48
#define IMX6SX_CLK_USDHC4_SEL 49
#define IMX6SX_CLK_SSI1_SEL 50
#define IMX6SX_CLK_SSI2_SEL 51
#define IMX6SX_CLK_SSI3_SEL 52
#define IMX6SX_CLK_QSPI1_SEL 53
#define IMX6SX_CLK_PERCLK_SEL 54
#define IMX6SX_CLK_VID_SEL 55
#define IMX6SX_CLK_ESAI_SEL 56
#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
#define IMX6SX_CLK_CAN_SEL 59
#define IMX6SX_CLK_UART_SEL 60
#define IMX6SX_CLK_QSPI2_SEL 61
#define IMX6SX_CLK_LDB_DI1_SEL 62
#define IMX6SX_CLK_LDB_DI0_SEL 63
#define IMX6SX_CLK_SPDIF_SEL 64
#define IMX6SX_CLK_AUDIO_SEL 65
#define IMX6SX_CLK_ENET_PRE_SEL 66
#define IMX6SX_CLK_ENET_SEL 67
#define IMX6SX_CLK_M4_PRE_SEL 68
#define IMX6SX_CLK_M4_SEL 69
#define IMX6SX_CLK_ECSPI_SEL 70
#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
#define IMX6SX_CLK_LCDIF1_SEL 73
#define IMX6SX_CLK_LCDIF2_SEL 74
#define IMX6SX_CLK_DISPLAY_SEL 75
#define IMX6SX_CLK_CSI_SEL 76
#define IMX6SX_CLK_CKO1_SEL 77
#define IMX6SX_CLK_CKO2_SEL 78
#define IMX6SX_CLK_CKO 79
#define IMX6SX_CLK_PERIPH_CLK2 80
#define IMX6SX_CLK_PERIPH2_CLK2 81
#define IMX6SX_CLK_IPG 82
#define IMX6SX_CLK_GPU_CORE_PODF 83
#define IMX6SX_CLK_GPU_AXI_PODF 84
#define IMX6SX_CLK_LCDIF1_PODF 85
#define IMX6SX_CLK_QSPI1_PODF 86
#define IMX6SX_CLK_EIM_SLOW_PODF 87
#define IMX6SX_CLK_LCDIF2_PODF 88
#define IMX6SX_CLK_PERCLK 89
#define IMX6SX_CLK_VID_PODF 90
#define IMX6SX_CLK_CAN_PODF 91
#define IMX6SX_CLK_USDHC1_PODF 92
#define IMX6SX_CLK_USDHC2_PODF 93
#define IMX6SX_CLK_USDHC3_PODF 94
#define IMX6SX_CLK_USDHC4_PODF 95
#define IMX6SX_CLK_UART_PODF 96
#define IMX6SX_CLK_ESAI_PRED 97
#define IMX6SX_CLK_ESAI_PODF 98
#define IMX6SX_CLK_SSI3_PRED 99
#define IMX6SX_CLK_SSI3_PODF 100
#define IMX6SX_CLK_SSI1_PRED 101
#define IMX6SX_CLK_SSI1_PODF 102
#define IMX6SX_CLK_QSPI2_PRED 103
#define IMX6SX_CLK_QSPI2_PODF 104
#define IMX6SX_CLK_SSI2_PRED 105
#define IMX6SX_CLK_SSI2_PODF 106
#define IMX6SX_CLK_SPDIF_PRED 107
#define IMX6SX_CLK_SPDIF_PODF 108
#define IMX6SX_CLK_AUDIO_PRED 109
#define IMX6SX_CLK_AUDIO_PODF 110
#define IMX6SX_CLK_ENET_PODF 111
#define IMX6SX_CLK_M4_PODF 112
#define IMX6SX_CLK_ECSPI_PODF 113
#define IMX6SX_CLK_LCDIF1_PRED 114
#define IMX6SX_CLK_LCDIF2_PRED 115
#define IMX6SX_CLK_DISPLAY_PODF 116
#define IMX6SX_CLK_CSI_PODF 117
#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
#define IMX6SX_CLK_LDB_DI0_DIV_7 119
#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
#define IMX6SX_CLK_LDB_DI1_DIV_7 121
#define IMX6SX_CLK_CKO1_PODF 122
#define IMX6SX_CLK_CKO2_PODF 123
#define IMX6SX_CLK_PERIPH 124
#define IMX6SX_CLK_PERIPH2 125
#define IMX6SX_CLK_OCRAM 126
#define IMX6SX_CLK_AHB 127
#define IMX6SX_CLK_MMDC_PODF 128
#define IMX6SX_CLK_ARM 129
#define IMX6SX_CLK_AIPS_TZ1 130
#define IMX6SX_CLK_AIPS_TZ2 131
#define IMX6SX_CLK_APBH_DMA 132
#define IMX6SX_CLK_ASRC_GATE 133
#define IMX6SX_CLK_CAAM_MEM 134
#define IMX6SX_CLK_CAAM_ACLK 135
#define IMX6SX_CLK_CAAM_IPG 136
#define IMX6SX_CLK_CAN1_IPG 137
#define IMX6SX_CLK_CAN1_SERIAL 138
#define IMX6SX_CLK_CAN2_IPG 139
#define IMX6SX_CLK_CAN2_SERIAL 140
#define IMX6SX_CLK_CPU_DEBUG 141
#define IMX6SX_CLK_DCIC1 142
#define IMX6SX_CLK_DCIC2 143
#define IMX6SX_CLK_AIPS_TZ3 144
#define IMX6SX_CLK_ECSPI1 145
#define IMX6SX_CLK_ECSPI2 146
#define IMX6SX_CLK_ECSPI3 147
#define IMX6SX_CLK_ECSPI4 148
#define IMX6SX_CLK_ECSPI5 149
#define IMX6SX_CLK_EPIT1 150
#define IMX6SX_CLK_EPIT2 151
#define IMX6SX_CLK_ESAI_EXTAL 152
#define IMX6SX_CLK_WAKEUP 153
#define IMX6SX_CLK_GPT_BUS 154
#define IMX6SX_CLK_GPT_SERIAL 155
#define IMX6SX_CLK_GPU 156
#define IMX6SX_CLK_OCRAM_S 157
#define IMX6SX_CLK_CANFD 158
#define IMX6SX_CLK_CSI 159
#define IMX6SX_CLK_I2C1 160
#define IMX6SX_CLK_I2C2 161
#define IMX6SX_CLK_I2C3 162
#define IMX6SX_CLK_OCOTP 163
#define IMX6SX_CLK_IOMUXC 164
#define IMX6SX_CLK_IPMUX1 165
#define IMX6SX_CLK_IPMUX2 166
#define IMX6SX_CLK_IPMUX3 167
#define IMX6SX_CLK_TZASC1 168
#define IMX6SX_CLK_LCDIF_APB 169
#define IMX6SX_CLK_PXP_AXI 170
#define IMX6SX_CLK_M4 171
#define IMX6SX_CLK_ENET 172
#define IMX6SX_CLK_DISPLAY_AXI 173
#define IMX6SX_CLK_LCDIF2_PIX 174
#define IMX6SX_CLK_LCDIF1_PIX 175
#define IMX6SX_CLK_LDB_DI0 176
#define IMX6SX_CLK_QSPI1 177
#define IMX6SX_CLK_MLB 178
#define IMX6SX_CLK_MMDC_P0_FAST 179
#define IMX6SX_CLK_MMDC_P0_IPG 180
#define IMX6SX_CLK_AXI 181
#define IMX6SX_CLK_PCIE_AXI 182
#define IMX6SX_CLK_QSPI2 183
#define IMX6SX_CLK_PER1_BCH 184
#define IMX6SX_CLK_PER2_MAIN 185
#define IMX6SX_CLK_PWM1 186
#define IMX6SX_CLK_PWM2 187
#define IMX6SX_CLK_PWM3 188
#define IMX6SX_CLK_PWM4 189
#define IMX6SX_CLK_GPMI_BCH_APB 190
#define IMX6SX_CLK_GPMI_BCH 191
#define IMX6SX_CLK_GPMI_IO 192
#define IMX6SX_CLK_GPMI_APB 193
#define IMX6SX_CLK_ROM 194
#define IMX6SX_CLK_SDMA 195
#define IMX6SX_CLK_SPBA 196
#define IMX6SX_CLK_SPDIF 197
#define IMX6SX_CLK_SSI1_IPG 198
#define IMX6SX_CLK_SSI2_IPG 199
#define IMX6SX_CLK_SSI3_IPG 200
#define IMX6SX_CLK_SSI1 201
#define IMX6SX_CLK_SSI2 202
#define IMX6SX_CLK_SSI3 203
#define IMX6SX_CLK_UART_IPG 204
#define IMX6SX_CLK_UART_SERIAL 205
#define IMX6SX_CLK_SAI1 206
#define IMX6SX_CLK_SAI2 207
#define IMX6SX_CLK_USBOH3 208
#define IMX6SX_CLK_USDHC1 209
#define IMX6SX_CLK_USDHC2 210
#define IMX6SX_CLK_USDHC3 211
#define IMX6SX_CLK_USDHC4 212
#define IMX6SX_CLK_EIM_SLOW 213
#define IMX6SX_CLK_PWM8 214
#define IMX6SX_CLK_VADC 215
#define IMX6SX_CLK_GIS 216
#define IMX6SX_CLK_I2C4 217
#define IMX6SX_CLK_PWM5 218
#define IMX6SX_CLK_PWM6 219
#define IMX6SX_CLK_PWM7 220
#define IMX6SX_CLK_CKO1 221
#define IMX6SX_CLK_CKO2 222
#define IMX6SX_CLK_IPP_DI0 223
#define IMX6SX_CLK_IPP_DI1 224
#define IMX6SX_CLK_ENET_AHB 225
#define IMX6SX_CLK_OCRAM_PODF 226
#define IMX6SX_CLK_GPT_3M 227
#define IMX6SX_CLK_ENET_PTP 228
#define IMX6SX_CLK_ENET_PTP_REF 229
#define IMX6SX_CLK_ENET2_REF 230
#define IMX6SX_CLK_ENET2_REF_125M 231
#define IMX6SX_CLK_AUDIO 232
#define IMX6SX_CLK_LVDS1_SEL 233
#define IMX6SX_CLK_LVDS1_OUT 234
#define IMX6SX_CLK_ASRC_IPG 235
#define IMX6SX_CLK_ASRC_MEM 236
#define IMX6SX_CLK_SAI1_IPG 237
#define IMX6SX_CLK_SAI2_IPG 238
#define IMX6SX_CLK_ESAI_IPG 239
#define IMX6SX_CLK_ESAI_MEM 240
#define IMX6SX_CLK_CLK_END 241
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
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