Commit 0c672aae authored by Shawn Guo's avatar Shawn Guo

clk: mxs: remove the use of mach level IO accessor

It removes the use of mach level IO accessor __mxs_setl/clrl, and hence
removes mach header inclusion from clock driver.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
parent 38d6590f
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <mach/mx23.h>
#include "clk.h" #include "clk.h"
static void __iomem *clkctrl; static void __iomem *clkctrl;
...@@ -52,10 +51,10 @@ static void __init clk_misc_init(void) ...@@ -52,10 +51,10 @@ static void __init clk_misc_init(void)
u32 val; u32 val;
/* Gate off cpu clock in WFI for power saving */ /* Gate off cpu clock in WFI for power saving */
__mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
/* Clear BYPASS for SAIF */ /* Clear BYPASS for SAIF */
__mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ); writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
/* SAIF has to use frac div for functional operation */ /* SAIF has to use frac div for functional operation */
val = readl_relaxed(SAIF); val = readl_relaxed(SAIF);
...@@ -66,14 +65,14 @@ static void __init clk_misc_init(void) ...@@ -66,14 +65,14 @@ static void __init clk_misc_init(void)
* Source ssp clock from ref_io than ref_xtal, * Source ssp clock from ref_io than ref_xtal,
* as ref_xtal only provides 24 MHz as maximum. * as ref_xtal only provides 24 MHz as maximum.
*/ */
__mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ); writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
/* /*
* 480 MHz seems too high to be ssp clock source directly, * 480 MHz seems too high to be ssp clock source directly,
* so set frac to get a 288 MHz ref_io. * so set frac to get a 288 MHz ref_io.
*/ */
__mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC); writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
__mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
} }
static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
......
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <mach/mx28.h>
#include "clk.h" #include "clk.h"
static void __iomem *clkctrl; static void __iomem *clkctrl;
...@@ -75,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux) ...@@ -75,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux)
if (clkmux > 0x3) if (clkmux > 0x3)
return -EINVAL; return -EINVAL;
__mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL); writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
__mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL); writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
return 0; return 0;
} }
...@@ -86,13 +85,13 @@ static void __init clk_misc_init(void) ...@@ -86,13 +85,13 @@ static void __init clk_misc_init(void)
u32 val; u32 val;
/* Gate off cpu clock in WFI for power saving */ /* Gate off cpu clock in WFI for power saving */
__mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
/* 0 is a bad default value for a divider */ /* 0 is a bad default value for a divider */
__mxs_setl(1 << BP_ENET_DIV_TIME, ENET); writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
/* Clear BYPASS for SAIF */ /* Clear BYPASS for SAIF */
__mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ); writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
/* SAIF has to use frac div for functional operation */ /* SAIF has to use frac div for functional operation */
val = readl_relaxed(SAIF0); val = readl_relaxed(SAIF0);
...@@ -112,7 +111,7 @@ static void __init clk_misc_init(void) ...@@ -112,7 +111,7 @@ static void __init clk_misc_init(void)
* Source ssp clock from ref_io than ref_xtal, * Source ssp clock from ref_io than ref_xtal,
* as ref_xtal only provides 24 MHz as maximum. * as ref_xtal only provides 24 MHz as maximum.
*/ */
__mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ); writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
/* /*
* 480 MHz seems too high to be ssp clock source directly, * 480 MHz seems too high to be ssp clock source directly,
......
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