Merge

arch/ppc/8260_io/Kconfig

 #
-# MPC8260 Communication options
+# CPM2 Communication options
 #
 
-menu "MPC8260 CPM Options"
-	depends on 8260
-
-config SCC_CONSOLE
-	bool "Enable SCC Console"
+menu "CPM2 Options"
+	depends on CPM2
 
 config SCC_ENET
 	bool "CPM SCC Ethernet"
@@ -24,19 +21,19 @@ config FCC1_ENET
 	bool "Ethernet on FCC1"
 	depends on FEC_ENET
 	help
-	  Use MPC8260 fast Ethernet controller 1 to drive Ethernet (default).
+	  Use CPM2 fast Ethernet controller 1 to drive Ethernet (default).
 
 config FCC2_ENET
 	bool "Ethernet on FCC2"
 	depends on FEC_ENET
 	help
-	  Use MPC8260 fast Ethernet controller 2 to drive Ethernet.
+	  Use CPM2 fast Ethernet controller 2 to drive Ethernet.
 
 config FCC3_ENET
 	bool "Ethernet on FCC3"
 	depends on FEC_ENET
 	help
-	  Use MPC8260 fast Ethernet controller 3 to drive Ethernet.
+	  Use CPM2 fast Ethernet controller 3 to drive Ethernet.
 
 config USE_MDIO
 	bool "Use MDIO for PHY configuration"

arch/ppc/8260_io/Makefile

 #
-# Makefile for the linux MPC8xx ppc-specific parts of comm processor
+# Makefile for the linux ppc-specific parts of comm processor (v2)
 #
 
-obj-y			:= commproc.o uart.o
-
 obj-$(CONFIG_FEC_ENET)	+= fcc_enet.o
 obj-$(CONFIG_SCC_ENET)	+= enet.o

arch/ppc/8260_io/enet.c

@@ -40,12 +40,12 @@
 #include <linux/skbuff.h>
 #include <linux/spinlock.h>
 
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/pgtable.h>
 #include <asm/mpc8260.h>
 #include <asm/bitops.h>
 #include <asm/uaccess.h>
-#include <asm/cpm_8260.h>
+#include <asm/cpm2.h>
 #include <asm/irq.h>
 
 /*
@@ -376,7 +376,7 @@ scc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 	    }
 
 	    if (must_restart) {
-		volatile cpm8260_t *cp;
+		volatile cpm_cpm2_t *cp;
 
 		/* Some transmit errors cause the transmitter to shut
 		 * down.  We now issue a restart transmit.  Since the
@@ -552,10 +552,10 @@ static void set_multicast_list(struct net_device *dev)
 	
 		/* Log any net taps. */
 		printk("%s: Promiscuous mode enabled.\n", dev->name);
-		cep->sccp->scc_pmsr |= SCC_PSMR_PRO;
+		cep->sccp->scc_psmr |= SCC_PSMR_PRO;
 	} else {
 
-		cep->sccp->scc_pmsr &= ~SCC_PSMR_PRO;
+		cep->sccp->scc_psmr &= ~SCC_PSMR_PRO;
 
 		if (dev->flags & IFF_ALLMULTI) {
 			/* Catch all multicast addresses, so set the
@@ -617,15 +617,15 @@ static int __init scc_enet_init(void)
 	unsigned long	mem_addr;
 	bd_t		*bd;
 	volatile	cbd_t		*bdp;
-	volatile	cpm8260_t	*cp;
+	volatile	cpm_cpm2_t	*cp;
 	volatile	scc_t		*sccp;
 	volatile	scc_enet_t	*ep;
-	volatile	immap_t		*immap;
-	volatile	iop8260_t	*io;
+	volatile	cpm2_map_t		*immap;
+	volatile	iop_cpm2_t	*io;
 
 	cp = cpmp;	/* Get pointer to Communication Processor */
 
-	immap = (immap_t *)IMAP_ADDR;	/* and to internal registers */
+	immap = (cpm2_map_t *)CPM_MAP_ADDR;	/* and to internal registers */
 	io = &immap->im_ioport;
 
 	bd = (bd_t *)__res;
@@ -680,11 +680,11 @@ static int __init scc_enet_init(void)
 	 * These are relative offsets in the DP ram address space.
 	 * Initialize base addresses for the buffer descriptors.
 	 */
-	i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
+	i = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
 	ep->sen_genscc.scc_rbase = i;
 	cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
 
-	i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
+	i = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
 	ep->sen_genscc.scc_tbase = i;
 	cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
 
@@ -820,7 +820,7 @@ static int __init scc_enet_init(void)
 	/* Set processing mode.  Use Ethernet CRC, catch broadcast, and
 	 * start frame search 22 bit times after RENA.
 	 */
-	sccp->scc_pmsr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
+	sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
 
 	/* It is now OK to enable the Ethernet transmitter.
 	 * Unfortunately, there are board implementation differences here.

arch/ppc/Kconfig

@@ -598,8 +598,16 @@ config TQM8260
 	  End of Life: not yet :-)
 	  URL: <http://www.denx.de/PDF/TQM82xx_SPEC_Rev005.pdf>
 
+config ADS8272
+	bool "ADS8272"
+
 endchoice
 
+config PQ2ADS
+	bool
+	depends on ADS8272
+	default y
+
 config TQM8xxL
 	bool
 	depends on 8xx && (TQM823L || TQM850L || FPS850L || TQM855L || TQM860L || SM850)
@@ -611,14 +619,32 @@ config EMBEDDEDBOOT
 	default y
 
 config 8260
-	bool "MPC8260 CPM Support" if WILLOW
+	bool "CPM2 Support" if WILLOW
 	depends on 6xx
 	default y if TQM8260 || RPXSUPER || EST8260 || SBS8260 || SBC82xx
 	help
-	  The MPC8260 CPM (Communications Processor Module) is a typical
-	  embedded CPU made by Motorola.  Selecting this option means that
-	  you wish to build a kernel for a machine with specifically an 8260
-	  for a CPU.
+	  The MPC8260 is a typical embedded CPU made by Motorola.  Selecting
+	  this option means that you wish to build a kernel for a machine with
+	  an 8260 class CPU.
+
+config 8272
+	bool
+	depends on 6xx
+	default y if ADS8272
+	select 8260
+	help
+	  The MPC8272 CPM has a different internal dpram setup than other CPM2
+	  devices
+
+config CPM2
+	bool
+	depends on 8260
+	default y
+	help
+	  The CPM2 (Communications Processor Module) is a coprocessor on
+	  embedded CPUs made by Motorola.  Selecting this option means that
+	  you wish to build a kernel for a machine with a CPM2 coprocessor
+	  on it (826x, 827x, 8560).
 
 config PPC_CHRP
 	bool
@@ -701,11 +727,11 @@ config SPRUCE_BAUD_33M
 
 config PC_KEYBOARD
 	bool "PC PS/2 style Keyboard"
-	depends on 4xx || 8260
+	depends on 4xx || CPM2
 
 config SERIAL_CONSOLE
 	bool
-	depends on 8xx || 8260
+	depends on 8xx
 	default y
 
 config SERIAL_CONSOLE_BAUD
@@ -986,7 +1012,7 @@ config ISA
 
 config GENERIC_ISA_DMA
 	bool
-	depends on POWER3 || POWER4 || 6xx && !8260
+	depends on POWER3 || POWER4 || 6xx && !CPM2
 	default y
 
 config EISA
@@ -1003,10 +1029,10 @@ config MCA
 	bool
 
 config PCI
-	bool "PCI support" if 40x || 8260 || 85xx
-	default y if !40x && !8260 && !8xx && !APUS && !85xx
-	default PCI_PERMEDIA if !4xx && !8260 && !8xx && APUS
-	default PCI_QSPAN if !4xx && !8260 && 8xx
+	default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
+	default PCI_QSPAN if !4xx && !CPM2 && 8xx
+	bool "PCI support" if 40x || CPM2 || 85xx
+	default y if !40x && !CPM2 && !8xx && !APUS && !85xx
 	help
 	  Find out whether your system includes a PCI bus. PCI is the name of
 	  a bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1019,11 +1045,39 @@ config PCI_DOMAINS
 
 config PCI_QSPAN
 	bool "QSpan PCI"
-	depends on !4xx && !8260 && 8xx
+	depends on !4xx && !CPM2 && 8xx
 	help
 	  Say Y here if you have a system based on a Motorola 8xx-series
 	  embedded processor with a QSPAN PCI interface, otherwise say N.
 
+config PCI_8260
+	bool
+	depends on PCI && 8260 && !8272
+	default y
+	
+config 8260_PCI9
+	bool "  Enable workaround for MPC826x erratum PCI 9"
+	depends on PCI_8260
+	default y
+
+choice 
+	prompt "  IDMA channel for PCI 9 workaround"
+	depends on 8260_PCI9
+
+config 8260_PCI9_IDMA1
+	bool "IDMA1"
+
+config 8260_PCI9_IDMA2
+	bool "IDMA2"
+
+config 8260_PCI9_IDMA3
+	bool "IDMA3"
+
+config 8260_PCI9_IDMA4
+	bool "IDMA4"
+
+endchoice
+
 config PCI_PERMEDIA
 	bool "PCI for Permedia2"
 	depends on !4xx && !8xx && APUS
@@ -1258,7 +1312,7 @@ endchoice
 
 config KGDB_CONSOLE
 	bool "Enable serial console thru kgdb port"
-	depends on KGDB && 8xx || 8260
+	depends on KGDB && 8xx || CPM2
 	help
 	  If you enable this, all serial console messages will be sent
 	  over the gdb stub.

arch/ppc/Makefile

@@ -48,7 +48,7 @@ core-$(CONFIG_XMON)		+= arch/ppc/xmon/
 core-$(CONFIG_APUS)		+= arch/ppc/amiga/
 drivers-$(CONFIG_8xx)		+= arch/ppc/8xx_io/
 drivers-$(CONFIG_4xx)		+= arch/ppc/4xx_io/
-drivers-$(CONFIG_8260)		+= arch/ppc/8260_io/
+drivers-$(CONFIG_CPM2)		+= arch/ppc/8260_io/
 
 BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd vmlinux.sm
 

arch/ppc/boot/simple/embed_config.c

@@ -16,7 +16,7 @@
 #endif
 #ifdef CONFIG_8260
 #include <asm/mpc8260.h>
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #endif
 #ifdef CONFIG_40x
 #include <asm/io.h>
@@ -415,9 +415,9 @@ clk_8260(bd_t *bd)
 {
 	uint	scmr, vco_out, clkin;
 	uint	plldf, pllmf, corecnf;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 	scmr = ip->im_clkrst.car_scmr;
 
 	/* The clkin is always bus frequency.
@@ -457,9 +457,9 @@ clk_8280(bd_t *bd)
 {
 	uint	scmr, main_clk, clkin;
 	uint	pllmf, corecnf;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 	scmr = ip->im_clkrst.car_scmr;
 
 	/* The clkin is always bus frequency.

arch/ppc/boot/simple/m8260_tty.c

@@ -3,7 +3,8 @@
  */
 #include <linux/types.h>
 #include <asm/mpc8260.h>
-#include <asm/cpm_8260.h>
+#include <asm/cpm2.h>
+#include <asm/immap_cpm2.h>
 
 uint	no_print;
 extern char	*params[];
@@ -29,12 +30,12 @@ serial_init(int ignored, bd_t *bd)
 	volatile scc_uart_t	*sup;
 #endif
 	volatile cbd_t	*tbdf, *rbdf;
-	volatile immap_t	*ip;
-	volatile iop8260_t	*io;
-	volatile cpm8260_t	*cp;
+	volatile cpm2_map_t	*ip;
+	volatile iop_cpm2_t	*io;
+	volatile cpm_cpm2_t	*cp;
 	uint	dpaddr, memaddr;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 	cp = &ip->im_cpm;
 	io = &ip->im_ioport;
 
@@ -223,10 +224,10 @@ serial_readbuf(u_char *cbuf)
 	volatile char		*buf;
 	volatile smc_uart_t	*up;
 	volatile scc_uart_t	*sup;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 	int	i, nc;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 
 #ifdef SCC_CONSOLE
 	sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
@@ -255,10 +256,10 @@ serial_putc(void *ignored, const char c)
 	volatile char		*buf;
 	volatile smc_uart_t	*up;
 	volatile scc_uart_t	*sup;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 	extern bd_t		*board_info;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 #ifdef SCC_CONSOLE
 	sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
 	tbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_tbase];
@@ -298,9 +299,9 @@ serial_tstc(void *ignored)
 	volatile cbd_t		*rbdf;
 	volatile smc_uart_t	*up;
 	volatile scc_uart_t	*sup;
-	volatile immap_t	*ip;
+	volatile cpm2_map_t	*ip;
 
-	ip = (immap_t *)IMAP_ADDR;
+	ip = (cpm2_map_t *)CPM_MAP_ADDR;
 #ifdef SCC_CONSOLE
 	sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
 	rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase];

arch/ppc/platforms/Makefile

@@ -30,6 +30,7 @@ obj-$(CONFIG_PPC_RTAS)		+= error_log.o proc_rtas.o
 obj-$(CONFIG_PREP_RESIDUAL)	+= residual.o
 obj-$(CONFIG_ADIR)		+= adir_setup.o adir_pic.o adir_pci.o
 obj-$(CONFIG_EST8260)		+= est8260_setup.o
+obj-$(CONFIG_PQ2ADS)		+= pq2ads_setup.o
 obj-$(CONFIG_TQM8260)		+= tqm8260_setup.o
 obj-$(CONFIG_EV64260)		+= ev64260_setup.o
 obj-$(CONFIG_GEMINI)		+= gemini_pci.o gemini_setup.o gemini_prom.o

arch/ppc/platforms/est8260.h

@@ -6,7 +6,7 @@
 #ifndef __EST8260_PLATFORM
 #define __EST8260_PLATFORM
 
-#define IMAP_ADDR		((uint)0xf0000000)
+#define CPM_MAP_ADDR		((uint)0xf0000000)
 
 #define BOOTROM_RESTART_ADDR	((uint)0xff000104)
 

arch/ppc/platforms/pq2ads.h

+/*
+ * A collection of structures, addresses, and values associated with
+ * the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
+ * Copied from the RPX-Classic and SBS8260 stuff.
+ *
+ * Copyright (c) 2001 Dan Malek (dan@mvista.com)
+ */
+#ifdef __KERNEL__
+#ifndef __MACH_ADS8260_DEFS
+#define __MACH_ADS8260_DEFS
+
+#include <linux/config.h>
+
+#include <asm/ppcboot.h>
+
+/* Memory map is configured by the PROM startup.
+ * We just map a few things we need.  The CSR is actually 4 byte-wide
+ * registers that can be accessed as 8-, 16-, or 32-bit values.
+ */
+#define CPM_MAP_ADDR		((uint)0xf0000000)
+#define BCSR_ADDR		((uint)0xf4500000)
+#define BCSR_SIZE		((uint)(32 * 1024))
+
+#define BOOTROM_RESTART_ADDR	((uint)0xff000104)
+
+/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
+ * only on word boundaries.
+ * Not all are used (yet), or are interesting to us (yet).
+ */
+
+/* Things of interest in the CSR.
+*/
+#define BCSR0_LED0		((uint)0x02000000)	/* 0 == on */
+#define BCSR0_LED1		((uint)0x01000000)	/* 0 == on */
+#define BCSR1_FETHIEN		((uint)0x08000000)	/* 0 == enable */
+#define BCSR1_FETH_RST		((uint)0x04000000)	/* 0 == reset */
+#define BCSR1_RS232_EN1		((uint)0x02000000)	/* 0 == enable */
+#define BCSR1_RS232_EN2		((uint)0x01000000)	/* 0 == enable */
+
+#define PHY_INTERRUPT	SIU_INT_IRQ7
+
+#ifdef CONFIG_PCI
+/* PCI interrupt controller */
+#define PCI_INT_STAT_REG	0xF8200000
+#define PCI_INT_MASK_REG	0xF8200004
+#define PIRQA			(NR_SIU_INTS + 0)
+#define PIRQB			(NR_SIU_INTS + 1)
+#define PIRQC			(NR_SIU_INTS + 2)
+#define PIRQD			(NR_SIU_INTS + 3)
+
+/*
+ * PCI memory map definitions for MPC8266ADS-PCI.
+ *
+ * processor view
+ *	local address		PCI address		target
+ *	0x80000000-0x9FFFFFFF	0x80000000-0x9FFFFFFF	PCI mem with prefetch
+ *	0xA0000000-0xBFFFFFFF	0xA0000000-0xBFFFFFFF	PCI mem w/o prefetch
+ *	0xF4000000-0xF7FFFFFF	0x00000000-0x03FFFFFF	PCI IO
+ *
+ * PCI master view
+ *	local address		PCI address		target
+ *	0x00000000-0x1FFFFFFF	0x00000000-0x1FFFFFFF	MPC8266 local memory
+ */
+
+/* window for a PCI master to access MPC8266 memory */
+#define PCI_SLV_MEM_LOCAL	0x00000000	/* Local base */
+#define PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
+
+/* window for the processor to access PCI memory with prefetching */
+#define PCI_MSTR_MEM_LOCAL	0x80000000	/* Local base */
+#define PCI_MSTR_MEM_BUS	0x80000000	/* PCI base   */
+#define PCI_MSTR_MEM_SIZE	0x20000000	/* 512MB */
+
+/* window for the processor to access PCI memory without prefetching */
+#define PCI_MSTR_MEMIO_LOCAL	0xA0000000	/* Local base */
+#define PCI_MSTR_MEMIO_BUS	0xA0000000	/* PCI base   */
+#define PCI_MSTR_MEMIO_SIZE	0x20000000	/* 512MB */
+
+/* window for the processor to access PCI I/O */
+#define PCI_MSTR_IO_LOCAL	0xF4000000	/* Local base */
+#define PCI_MSTR_IO_BUS         0x00000000	/* PCI base   */
+#define PCI_MSTR_IO_SIZE        0x04000000	/* 64MB */
+
+#define _IO_BASE		PCI_MSTR_IO_LOCAL
+#define _ISA_MEM_BASE		PCI_MSTR_MEMIO_LOCAL
+#define PCI_DRAM_OFFSET		PCI_SLV_MEM_BUS
+#endif /* CONFIG_PCI */
+
+#endif /* __MACH_ADS8260_DEFS */
+#endif /* __KERNEL__ */

arch/ppc/platforms/pq2ads_setup.c

+/*
+ * arch/ppc/platforms/pq2ads_setup.c
+ *
+ * PQ2ADS platform support
+ *
+ * Author: Kumar Gala <kumar.gala@freescale.com>
+ * Derived from: est8260_setup.c by Allen Curtis
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/seq_file.h>
+
+#include <asm/mpc8260.h>
+#include <asm/machdep.h>
+
+static void (*callback_setup_arch)(void);
+
+extern unsigned char __res[sizeof(bd_t)];
+
+extern void m8260_init(unsigned long r3, unsigned long r4,
+	unsigned long r5, unsigned long r6, unsigned long r7);
+
+static int
+pq2ads_show_cpuinfo(struct seq_file *m)
+{
+	bd_t	*binfo = (bd_t *)__res;
+
+	seq_printf(m, "vendor\t\t: Motorola\n"
+		      "machine\t\t: PQ2 ADS PowerPC\n"
+		      "\n"
+		      "mem size\t\t: 0x%08lx\n"
+		      "console baud\t\t: %ld\n"
+		      "\n",
+		      binfo->bi_memsize,
+		      binfo->bi_baudrate);
+	return 0;
+}
+
+static void __init
+pq2ads_setup_arch(void)
+{
+	printk("PQ2 ADS Port\n");
+	callback_setup_arch();
+        *(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_RS232_EN2;
+}
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
+{
+	/* Generic 8260 platform initialization */
+	m8260_init(r3, r4, r5, r6, r7);
+
+	/* Anything special for this platform */
+	ppc_md.show_cpuinfo	= pq2ads_show_cpuinfo;
+
+	callback_setup_arch	= ppc_md.setup_arch;
+	ppc_md.setup_arch	= pq2ads_setup_arch;
+}

arch/ppc/platforms/rpxsuper.h

@@ -32,7 +32,7 @@ extern bd_t m8xx_board_info;
  * We just map a few things we need.  The CSR is actually 4 byte-wide
  * registers that can be accessed as 8-, 16-, or 32-bit values.
  */
-#define IMAP_ADDR		((uint)0xf0000000)
+#define CPM_MAP_ADDR		((uint)0xf0000000)
 #define RPX_CSR_ADDR		((uint)0xfa000000)
 #define RPX_CSR_SIZE		((uint)(512 * 1024))
 #define RPX_NVRTC_ADDR		((uint)0xfa080000)

arch/ppc/platforms/sbc82xx.c

@@ -18,14 +18,18 @@
 #include <linux/config.h>
 #include <linux/seq_file.h>
 #include <linux/stddef.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
 
 #include <asm/mpc8260.h>
 #include <asm/machdep.h>
 #include <asm/io.h>
 #include <asm/todc.h>
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
+#include <asm/pci.h>
 
 static void (*callback_setup_arch)(void);
+static void (*callback_init_IRQ)(void);
 
 extern unsigned char __res[sizeof(bd_t)];
 
@@ -57,6 +61,7 @@ sbc82xx_setup_arch(void)
 	callback_setup_arch();
 }
 
+#ifdef CONFIG_GEN_RTC
 TODC_ALLOC();
 
 /*
@@ -64,16 +69,17 @@ TODC_ALLOC();
  * directly use ioremap() at that time.
  * late_time_init() is call after paging init.
  */
-#ifdef CONFIG_GEN_RTC
+
 static void sbc82xx_time_init(void)
 {
-	volatile memctl8260_t *mc = &immr->im_memctl;
-	TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
+	volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
 
 	/* Set up CS11 for RTC chip */
 	mc->memc_br11=0;
 	mc->memc_or11=0xffff0836;
-	mc->memc_br11=0x80000801;
+	mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
+
+	TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
 
 	todc_info->nvram_data =
 		(unsigned int)ioremap(todc_info->nvram_data, 0x2000);
@@ -86,6 +92,152 @@ static void sbc82xx_time_init(void)
 }
 #endif /* CONFIG_GEN_RTC */
 
+static volatile char *sbc82xx_i8259_map;
+static char sbc82xx_i8259_mask = 0xff;
+static spinlock_t sbc82xx_i8259_lock = SPIN_LOCK_UNLOCKED;
+
+static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	irq_nr -= NR_SIU_INTS;
+
+	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
+	sbc82xx_i8259_mask |= 1 << irq_nr;
+	(void) sbc82xx_i8259_map[1];	/* Dummy read */
+	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
+	sbc82xx_i8259_map[0] = 0x20;	/* OCW2: Non-specific EOI */
+	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
+}
+
+static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	irq_nr -= NR_SIU_INTS;
+
+	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
+	sbc82xx_i8259_mask |= 1 << irq_nr;
+	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
+	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
+}
+
+static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
+{
+	unsigned long flags;
+
+	irq_nr -= NR_SIU_INTS;
+
+	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
+	sbc82xx_i8259_mask &= ~(1 << irq_nr);
+	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
+	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
+}
+
+static void sbc82xx_i8259_end_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
+	    && irq_desc[irq].action)
+		sbc82xx_i8259_unmask_irq(irq);
+}
+
+
+struct hw_interrupt_type sbc82xx_i8259_ic = {
+	.typename = " i8259     ",
+	.enable = sbc82xx_i8259_unmask_irq,
+	.disable = sbc82xx_i8259_mask_irq,
+	.ack = sbc82xx_i8259_mask_and_ack_irq,
+	.end = sbc82xx_i8259_end_irq,
+};
+
+static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+	spin_lock(&sbc82xx_i8259_lock);
+
+	sbc82xx_i8259_map[0] = 0x0c;	/* OCW3: Read IR register on RD# pulse */
+	irq = sbc82xx_i8259_map[0] & 7;	/* Read IRR */
+
+	if (irq == 7) {
+		/* Possible spurious interrupt */
+		int isr;
+		sbc82xx_i8259_map[0] = 0x0b;	/* OCW3: Read IS register on RD# pulse */
+		isr = sbc82xx_i8259_map[0];	/* Read ISR */
+
+		if (!(isr & 0x80)) {
+			printk(KERN_INFO "Spurious i8259 interrupt\n");
+			return IRQ_HANDLED;
+		}
+	}
+	ppc_irq_dispatch_handler(regs, NR_SIU_INTS + irq);
+	return IRQ_HANDLED;
+}
+
+void __init sbc82xx_init_IRQ(void)
+{
+	volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
+	volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
+	int i;
+
+	callback_init_IRQ();
+
+	/* u-boot doesn't always set the board up correctly */
+	mc->memc_br5 = 0;
+	mc->memc_or5 = 0xfff00856;
+	mc->memc_br5 = 0x22000801;
+
+	sbc82xx_i8259_map = ioremap(0x22008000, 2);
+	if (!sbc82xx_i8259_map) {
+		printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
+		return;
+	}
+	
+	/* Set up the interrupt handlers for the i8259 IRQs */
+	for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
+                irq_desc[i].handler = &sbc82xx_i8259_ic;
+		irq_desc[i].status |= IRQ_LEVEL;
+	}
+
+	/* make IRQ6 level sensitive */
+	ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
+	irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
+
+	/* Initialise the i8259 */
+	sbc82xx_i8259_map[0] = 0x1b;	/* ICW1: Level, no cascade, ICW4 */
+	sbc82xx_i8259_map[1] = 0x00;	/* ICW2: vector base */
+					/* No ICW3 (no cascade) */
+	sbc82xx_i8259_map[1] = 0x01;	/* ICW4: 8086 mode, normal EOI */
+
+	sbc82xx_i8259_map[0] = 0x0b;	/* OCW3: Read IS register on RD# pulse */
+
+	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
+
+	/* Request cascade IRQ */
+	if (request_irq(SIU_INT_IRQ6, sbc82xx_i8259_demux, SA_INTERRUPT,
+			"i8259 demux", 0)) {
+		printk("Installation of i8259 IRQ demultiplexer failed.\n");
+	}
+}
+
+static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
+			       unsigned char pin)
+{
+	static char pci_irq_table[][4] = {
+		/*
+		 * PCI IDSEL/INTPIN->INTLINE
+		 *  A      B      C      D
+		 */
+		{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD },	/* IDSEL 16 - PMC slot */
+		{ SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1,  -1  },			/* IDSEL 17 - CardBus */
+		{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
+	};
+
+	const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
+
+	return PCI_IRQ_TABLE_LOOKUP;
+}
+
+
+
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	      unsigned long r6, unsigned long r7)
@@ -101,7 +253,11 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	ppc_md.show_cpuinfo	= sbc82xx_show_cpuinfo;
 
 	callback_setup_arch	= ppc_md.setup_arch;
+	callback_init_IRQ	= ppc_md.init_IRQ;
+
 	ppc_md.setup_arch	= sbc82xx_setup_arch;
+	ppc_md.init_IRQ		= sbc82xx_init_IRQ;
+	ppc_md.pci_map_irq	= sbc82xx_pci_map_irq;
 #ifdef CONFIG_GEN_RTC
 	ppc_md.time_init        = NULL;
 	ppc_md.get_rtc_time     = NULL;

arch/ppc/platforms/sbc82xx.h

@@ -9,10 +9,9 @@
 
 #include <asm/ppcboot.h>
 
-#define IMAP_ADDR			0xf0000000
 #define CPM_MAP_ADDR			0xf0000000
 
-#define SBC82xx_TODC_NVRAM_ADDR		0x80000000
+#define SBC82xx_TODC_NVRAM_ADDR		0xd0000000
 
 #define SBC82xx_MACADDR_NVRAM_FCC1	0x220000c9	/* JP6B */
 #define SBC82xx_MACADDR_NVRAM_SCC1	0x220000cf	/* JP6A */
@@ -21,4 +20,13 @@
 
 #define BOOTROM_RESTART_ADDR      ((uint)0x40000104)
 
+#define SBC82xx_PC_IRQA (NR_SIU_INTS+0)
+#define SBC82xx_PC_IRQB (NR_SIU_INTS+1)
+#define SBC82xx_MPC185_IRQ (NR_SIU_INTS+2)
+#define SBC82xx_ATM_IRQ (NR_SIU_INTS+3)
+#define SBC82xx_PIRQA (NR_SIU_INTS+4)
+#define SBC82xx_PIRQB (NR_SIU_INTS+5)
+#define SBC82xx_PIRQC (NR_SIU_INTS+6)
+#define SBC82xx_PIRQD (NR_SIU_INTS+7)
+
 #endif /* __PPC_SBC82xx_H__ */

arch/ppc/platforms/sbs8260.h

@@ -5,7 +5,7 @@
  * the configuration SCMR and the Power-On-Reset word.
  */
 
-#define IMAP_ADDR	((uint)0xfe000000)
+#define CPM_MAP_ADDR	((uint)0xfe000000)
 
 
 /* A Board Information structure that is given to a program when

arch/ppc/platforms/tqm8260.h

@@ -11,7 +11,7 @@
 
 #include <asm/ppcboot.h>
 
-#define IMAP_ADDR		((uint)0xFFF00000)
+#define CPM_MAP_ADDR		((uint)0xFFF00000)
 #define PHY_INTERRUPT		25
 
 #define BOOTROM_RESTART_ADDR	((uint)0x40000104)

arch/ppc/platforms/tqm8260_setup.c

@@ -17,7 +17,7 @@
 #include <linux/config.h>
 #include <linux/seq_file.h>
 
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/mpc8260.h>
 #include <asm/machdep.h>
 
@@ -44,8 +44,8 @@ tqm8260_show_cpuinfo(struct seq_file *m)
 static int
 tqm8260_set_rtc_time(unsigned long time)
 {
-	((immap_t *)IMAP_ADDR)->im_sit.sit_tmcnt = time;
-	((immap_t *)IMAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
+	((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt = time;
+	((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
 
 	return(0);
 }
@@ -53,7 +53,7 @@ tqm8260_set_rtc_time(unsigned long time)
 static unsigned long
 tqm8260_get_rtc_time(void)
 {
-	return ((immap_t *)IMAP_ADDR)->im_sit.sit_tmcnt;
+	return ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt;
 }
 
 static void __init

arch/ppc/syslib/Makefile

@@ -69,7 +69,10 @@ obj-$(CONFIG_SANDPOINT)		+= i8259.o open_pic.o pci_auto.o todc_time.o
 obj-$(CONFIG_SBC82xx)		+= todc_time.o
 obj-$(CONFIG_SPRUCE)		+= cpc700_pic.o indirect_pci.o pci_auto.o \
 				   todc_time.o
-obj-$(CONFIG_8260)		+= m8260_setup.o ppc8260_pic.o
+obj-$(CONFIG_8260)		+= m8260_setup.o cpm2_pic.o
+obj-$(CONFIG_PCI_8260)		+= m8260_pci.o indirect_pci.o
+obj-$(CONFIG_8260_PCI9)		+= m8260_pci_erratum9.o
+obj-$(CONFIG_CPM2)		+= cpm2_common.o
 ifeq ($(CONFIG_PPC_GEN550),y)
 obj-$(CONFIG_KGDB)		+= gen550_kgdb.o gen550_dbg.o
 obj-$(CONFIG_SERIAL_TEXT_DEBUG)	+= gen550_dbg.o

arch/ppc/8260_io/commproc.c → arch/ppc/syslib/cpm2_common.c

@@ -26,29 +26,26 @@
 #include <asm/mpc8260.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/immap_8260.h>
-#include <asm/cpm_8260.h>
+#include <asm/immap_cpm2.h>
+#include <asm/cpm2.h>
 
 static	uint	dp_alloc_base;	/* Starting offset in DP ram */
 static	uint	dp_alloc_top;	/* Max offset + 1 */
 static	uint	host_buffer;	/* One page of host buffer */
 static	uint	host_end;	/* end + 1 */
-cpm8260_t	*cpmp;		/* Pointer to comm processor space */
+cpm_cpm2_t	*cpmp;		/* Pointer to comm processor space */
 
 /* We allocate this here because it is used almost exclusively for
  * the communication processor devices.
  */
-immap_t		*immr;
+cpm2_map_t *cpm2_immr;
 
 void
-m8260_cpm_reset(void)
+cpm2_reset(void)
 {
-	volatile immap_t	 *imp;
-	volatile cpm8260_t	*commproc;
-	uint			vpgaddr;
+	uint vpgaddr;
 
-	immr = imp = (volatile immap_t *)IMAP_ADDR;
-	commproc = &imp->im_cpm;
+	cpm2_immr = (cpm2_map_t *)CPM_MAP_ADDR;
 
 	/* Reclaim the DP memory for our use.
 	*/
@@ -65,7 +62,7 @@ m8260_cpm_reset(void)
 
 	/* Tell everyone where the comm processor resides.
 	*/
-	cpmp = (cpm8260_t *)commproc;
+	cpmp = &cpm2_immr->im_cpm;
 }
 
 /* Allocate some memory from the dual ported ram.
@@ -73,7 +70,7 @@ m8260_cpm_reset(void)
  * if they ask.
  */
 uint
-m8260_cpm_dpalloc(uint size, uint align)
+cpm2_dpalloc(uint size, uint align)
 {
 	uint	retloc;
 	uint	align_mask, off;
@@ -100,7 +97,7 @@ m8260_cpm_dpalloc(uint size, uint align)
  * UART "fifos" and the like.
  */
 uint
-m8260_cpm_hostalloc(uint size, uint align)
+cpm2_hostalloc(uint size, uint align)
 {
 	uint	retloc;
 	uint	align_mask, off;
@@ -140,17 +137,17 @@ m8260_cpm_hostalloc(uint size, uint align)
  * oversampled clock.
  */
 void
-m8260_cpm_setbrg(uint brg, uint rate)
+cpm2_setbrg(uint brg, uint rate)
 {
 	volatile uint	*bp;
 
 	/* This is good enough to get SMCs running.....
 	*/
 	if (brg < 4) {
-		bp = (uint *)&immr->im_brgc1;
+		bp = (uint *)&cpm2_immr->im_brgc1;
 	}
 	else {
-		bp = (uint *)&immr->im_brgc5;
+		bp = (uint *)&cpm2_immr->im_brgc5;
 		brg -= 4;
 	}
 	bp += brg;
@@ -161,15 +158,15 @@ m8260_cpm_setbrg(uint brg, uint rate)
  * clocks.
  */
 void
-m8260_cpm_fastbrg(uint brg, uint rate, int div16)
+cpm2_fastbrg(uint brg, uint rate, int div16)
 {
 	volatile uint	*bp;
 
 	if (brg < 4) {
-		bp = (uint *)&immr->im_brgc1;
+		bp = (uint *)&cpm2_immr->im_brgc1;
 	}
 	else {
-		bp = (uint *)&immr->im_brgc5;
+		bp = (uint *)&cpm2_immr->im_brgc5;
 		brg -= 4;
 	}
 	bp += brg;

arch/ppc/syslib/ppc8260_pic.c → arch/ppc/syslib/cpm2_pic.c

@@ -3,11 +3,11 @@
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <asm/irq.h>
-#include <asm/immap_8260.h>
+#include <asm/immap_cpm2.h>
 #include <asm/mpc8260.h>
-#include "ppc8260_pic.h"
+#include "cpm2_pic.h"
 
-/* The 8260 internal interrupt controller.  It is usually
+/* The CPM2 internal interrupt controller.  It is usually
  * the only interrupt controller.
  * There are two 32-bit registers (high/low) for up to 64
  * possible interrupts.
@@ -40,7 +40,7 @@ static	u_char	irq_to_siubit[] = {
 	 7,  6,  5,  4,  3,  2,  1,  0
 };
 
-static void m8260_mask_irq(unsigned int irq_nr)
+static void cpm2_mask_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -48,12 +48,12 @@ static void m8260_mask_irq(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(immr->im_intctl.ic_simrh);
+	simr = &(cpm2_immr->im_intctl.ic_simrh);
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 }
 
-static void m8260_unmask_irq(unsigned int irq_nr)
+static void cpm2_unmask_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -61,12 +61,12 @@ static void m8260_unmask_irq(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(immr->im_intctl.ic_simrh);
+	simr = &(cpm2_immr->im_intctl.ic_simrh);
 	ppc_cached_irq_mask[word] |= (1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 }
 
-static void m8260_mask_and_ack(unsigned int irq_nr)
+static void cpm2_mask_and_ack(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr, *sipnr;
@@ -74,14 +74,14 @@ static void m8260_mask_and_ack(unsigned int irq_nr)
 	bit = irq_to_siubit[irq_nr];
 	word = irq_to_siureg[irq_nr];
 
-	simr = &(immr->im_intctl.ic_simrh);
-	sipnr = &(immr->im_intctl.ic_sipnrh);
+	simr = &(cpm2_immr->im_intctl.ic_simrh);
+	sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
 	simr[word] = ppc_cached_irq_mask[word];
 	sipnr[word] = 1 << (31 - bit);
 }
 
-static void m8260_end_irq(unsigned int irq_nr)
+static void cpm2_end_irq(unsigned int irq_nr)
 {
 	int	bit, word;
 	volatile uint	*simr;
@@ -92,33 +92,33 @@ static void m8260_end_irq(unsigned int irq_nr)
 		bit = irq_to_siubit[irq_nr];
 		word = irq_to_siureg[irq_nr];
 
-		simr = &(immr->im_intctl.ic_simrh);
+		simr = &(cpm2_immr->im_intctl.ic_simrh);
 		ppc_cached_irq_mask[word] |= (1 << (31 - bit));
 		simr[word] = ppc_cached_irq_mask[word];
 	}
 }
 
-struct hw_interrupt_type ppc8260_pic = {
-	" 8260 SIU  ",
+struct hw_interrupt_type cpm2_pic = {
+	" CPM2 SIU  ",
 	NULL,
 	NULL,
-	m8260_unmask_irq,
-	m8260_mask_irq,
-	m8260_mask_and_ack,
-	m8260_end_irq,
+	cpm2_unmask_irq,
+	cpm2_mask_irq,
+	cpm2_mask_and_ack,
+	cpm2_end_irq,
 	0
 };
 
 
 int
-m8260_get_irq(struct pt_regs *regs)
+cpm2_get_irq(struct pt_regs *regs)
 {
 	int irq;
         unsigned long bits;
 
-        /* For MPC8260, read the SIVEC register and shift the bits down
+        /* For CPM2, read the SIVEC register and shift the bits down
          * to get the irq number.         */
-        bits = immr->im_intctl.ic_sivec;
+        bits = cpm2_immr->im_intctl.ic_sivec;
         irq = bits >> 26;
 
 	if (irq == 0)

arch/ppc/syslib/cpm2_pic.h

+#ifndef _PPC_KERNEL_CPM2_H
+#define _PPC_KERNEL_CPM2_H
+
+#include <linux/irq.h>
+
+extern struct hw_interrupt_type cpm2_pic;
+
+void cpm2_pic_init(void);
+void cpm2_do_IRQ(struct pt_regs *regs,
+                 int            cpu);
+int cpm2_get_irq(struct pt_regs *regs);
+
+#endif /* _PPC_KERNEL_CPM2_H */

arch/ppc/syslib/ppc8260_pic.h

-#ifndef _PPC_KERNEL_PPC8260_H
-#define _PPC_KERNEL_PPC8260_H
-
-#include <linux/irq.h>
-
-extern struct hw_interrupt_type ppc8260_pic;
-
-void m8260_pic_init(void);
-void m8260_do_IRQ(struct pt_regs *regs,
-                 int            cpu);
-int m8260_get_irq(struct pt_regs *regs);
-
-#endif /* _PPC_KERNEL_PPC8260_H */