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Commit 0d6cde50 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx into next/dt 

Merge "NXP LPC32xx device tree updates for v4.7" from Vladimir Zapolskiy:

This includes a few functional changes:
* new representation of MIC, SIC1 and SIC2 interrupt controllers,
* disabled by default SPI1, SPI2, SSP0 and SSP1 SPI controllers in
  shared lpc32xx.dtsi file,
* added clock sources for SPI1 and SPI2,
* set default clock rate of HCLK PLL to main osc rate multiplied by 16.

Also there are some non-functional changes:
* flatten board DTS files by exploiting device node labels,
* add 'partitions' device node for NAND SLC / MTD OF,
* correct Atmel vendor prefix to describe on board AT24 EEPROMs,
* rename board DTS files by adding SoC name prefix.

Since now DTS files of LPC32xx boards match "^lpc32[2345]0-" pattern.

* tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx:
  ARM: dts: lpc32xx: phy3250: add SoC name prefix to board dts file
  ARM: dts: lpc32xx: phy3250: add NAND partitions device node
  ARM: dts: lpc32xx: phy3250: avoid extension of device nodes by absolute path
  ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file
  ARM: dts: lpc32xx: ea3250: fix Atmel at24 eeprom vendor
  ARM: dts: lpc32xx: ea3250: add NAND partitions device node
  ARM: dts: lpc32xx: ea3250: avoid extension of device nodes by absolute path
  ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
  dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
  ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default
  ARM: dts: phy3250: enable ssp0
  ARM: dts: lpc32xx: add clock properties to spi nodes
  ARM: dts: lpc32xx: set default clock rate of HCLK PLL
parents ff83b377 3ff11fe8
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Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
View file @ 0d6cde50
* NXP LPC32xx Main Interrupt Controller
(MIC, including SIC1 and SIC2 secondary controllers)
* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
Required properties:
- compatible: Should be "nxp,lpc3220-mic"
- interrupt-controller: Identifies the node as an interrupt controller.
- interrupt-parent: Empty for the interrupt controller itself
- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
The first cell is the IRQ number
The second cell is used to specify mode:
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Default for internal sources should be set to 4 (active high).
- reg: Should contain MIC registers location and length
- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
- reg: should contain IC registers location and length.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: the number of cells to define an interrupt, should be 2.
The first cell is the IRQ number, the second cell is used to specify
one of the supported IRQ types:
IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
Reset value is IRQ_TYPE_LEVEL_LOW.
Optional properties:
- interrupt-parent: empty for MIC interrupt controller, link to parent
MIC interrupt controller for SIC1 and SIC2
- interrupts: empty for MIC interrupt controller, cascaded MIC
hardware interrupts for SIC1 and SIC2
Examples:
/*
* MIC
*/
/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
reg = <0x40008000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
};
sic1: interrupt-controller@4000c000 {
compatible = "nxp,lpc3220-sic";
reg = <0x4000c000 0x4000>;
interrupt-controller;
interrupt-parent;
#interrupt-cells = <2>;
reg = <0x40008000 0xC000>;
interrupt-parent = <&mic>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
<30 IRQ_TYPE_LEVEL_LOW>;
};
/*
* ADC
*/
sic2: interrupt-controller@40010000 {
compatible = "nxp,lpc3220-sic";
reg = <0x40010000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
};
/* ADC */
adc@40048000 {
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupt-parent = <&mic>;
interrupts = <39 4>;
interrupt-parent = <&sic1>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
};
arch/arm/boot/dts/Makefile
View file @ 0d6cde50
......@@ -245,7 +245,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \
lpc4350-hitex-eval.dtb \
lpc4357-ea4357-devkit.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += \
ea3250.dtb phy3250.dtb
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_MACH_MESON8) += \
......
arch/arm/boot/dts/ea3250.dts → arch/arm/boot/dts/lpc3250-ea3250.dts
View file @ 0d6cde50
......@@ -25,119 +25,6 @@ memory {
reg = <0x80000000 0x4000000>;
};
ahb {
mac: ethernet@31060000 {
phy-mode = "rmii";
use-iram;
};
/* 128MB Flash via SLC NAND controller */
slc: flash@20020000 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
nxp,wdr-clks = <14>;
nxp,wwidth = <260000000>;
nxp,whold = <104000000>;
nxp,wsetup = <200000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <34666666>;
nxp,rhold = <104000000>;
nxp,rsetup = <200000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
mtd0@00000000 {
label = "ea3250-boot";
reg = <0x00000000 0x00080000>;
read-only;
};
mtd1@00080000 {
label = "ea3250-uboot";
reg = <0x00080000 0x000c0000>;
read-only;
};
mtd2@00140000 {
label = "ea3250-kernel";
reg = <0x00140000 0x00400000>;
};
mtd3@00540000 {
label = "ea3250-rootfs";
reg = <0x00540000 0x07ac0000>;
};
};
apb {
uart5: serial@40090000 {
status = "okay";
};
uart3: serial@40080000 {
status = "okay";
};
uart6: serial@40098000 {
status = "okay";
};
i2c1: i2c@400A0000 {
clock-frequency = <100000>;
eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
eeprom@57 {
compatible = "at,24c64";
reg = <0x57>;
};
uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 0x59 0>;
reset-gpio = <&gpio 0x51 0>;
dac-clk = "wspll";
};
pca9532: pca9532@60 {
compatible = "nxp,pca9532";
gpio-controller;
#gpio-cells = <2>;
reg = <0x60>;
};
};
i2c2: i2c@400A8000 {
clock-frequency = <100000>;
};
sd@20098000 {
wp-gpios = <&pca9532 5 0>;
cd-gpios = <&pca9532 4 0>;
cd-inverted;
bus-width = <4>;
status = "okay";
};
};
fab {
uart1: serial@40014000 {
status = "okay";
};
/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
adc@40048000 {
status = "okay";
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
......@@ -258,12 +145,44 @@ lede8 {
};
};
/* Here, choose exactly one from: ohci, usbd */
&ohci /* &usbd */ {
transceiver = <&isp1301>;
/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
&adc {
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 0x59 0>;
reset-gpio = <&gpio 0x51 0>;
dac-clk = "wspll";
};
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
pca9532: pca9532@60 {
compatible = "nxp,pca9532";
gpio-controller;
#gpio-cells = <2>;
reg = <0x60>;
};
};
&i2c2 {
clock-frequency = <100000>;
};
&i2cusb {
clock-frequency = <100000>;
......@@ -272,3 +191,82 @@ isp1301: usb-transceiver@2d {
reg = <0x2d>;
};
};
&mac {
phy-mode = "rmii";
use-iram;
};
/* Here, choose exactly one from: ohci, usbd */
&ohci /* &usbd */ {
transceiver = <&isp1301>;
status = "okay";
};
&sd {
wp-gpios = <&pca9532 5 0>;
cd-gpios = <&pca9532 4 0>;
cd-inverted;
bus-width = <4>;
status = "okay";
};
/* 128MB Flash via SLC NAND controller */
&slc {
status = "okay";
nxp,wdr-clks = <14>;
nxp,wwidth = <260000000>;
nxp,whold = <104000000>;
nxp,wsetup = <200000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <34666666>;
nxp,rhold = <104000000>;
nxp,rsetup = <200000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
mtd0@00000000 {
label = "ea3250-boot";
reg = <0x00000000 0x00080000>;
read-only;
};
mtd1@00080000 {
label = "ea3250-uboot";
reg = <0x00080000 0x000c0000>;
read-only;
};
mtd2@00140000 {
label = "ea3250-kernel";
reg = <0x00140000 0x00400000>;
};
mtd3@00540000 {
label = "ea3250-rootfs";
reg = <0x00540000 0x07ac0000>;
};
};
};
&uart1 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart5 {
status = "okay";
};
&uart6 {
status = "okay";
};
arch/arm/boot/dts/phy3250.dts → arch/arm/boot/dts/lpc3250-phy3250.dts
View file @ 0d6cde50
......@@ -56,146 +56,6 @@ sd_reg: regulator@2 {
};
};
ahb {
mac: ethernet@31060000 {
phy-mode = "rmii";
use-iram;
};
clcd@31040000 {
status = "okay";
};
/* 64MB Flash via SLC NAND controller */
slc: flash@20020000 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
nxp,wdr-clks = <14>;
nxp,wwidth = <40000000>;
nxp,whold = <100000000>;
nxp,wsetup = <100000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <40000000>;
nxp,rhold = <66666666>;
nxp,rsetup = <100000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
mtd0@00000000 {
label = "phy3250-boot";
reg = <0x00000000 0x00064000>;
read-only;
};
mtd1@00064000 {
label = "phy3250-uboot";
reg = <0x00064000 0x00190000>;
read-only;
};
mtd2@001f4000 {
label = "phy3250-ubt-prms";
reg = <0x001f4000 0x00010000>;
};
mtd3@00204000 {
label = "phy3250-kernel";
reg = <0x00204000 0x00400000>;
};
mtd4@00604000 {
label = "phy3250-rootfs";
reg = <0x00604000 0x039fc000>;
};
};
apb {
uart5: serial@40090000 {
status = "okay";
};
uart3: serial@40080000 {
status = "okay";
};
i2c1: i2c@400A0000 {
clock-frequency = <100000>;
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 0x59 0>;
reset-gpio = <&gpio 0x51 0>;
dac-clk = "wspll";
};
};
i2c2: i2c@400A8000 {
clock-frequency = <100000>;
};
ssp0: ssp@20084000 {
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
cs-gpios = <&gpio 3 5 0>;
eeprom: at25@0 {
pl022,interface = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
at25,byte-len = <0x8000>;
at25,addr-mode = <2>;
at25,page-size = <64>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
};
};
sd@20098000 {
wp-gpios = <&gpio 3 0 0>;
cd-gpios = <&gpio 3 1 0>;
cd-inverted;
bus-width = <4>;
vmmc-supply = <&sd_reg>;
status = "okay";
};
};
fab {
uart2: serial@40018000 {
status = "okay";
};
tsc@40048000 {
status = "okay";
};
key@40050000 {
status = "okay";
keypad,num-rows = <1>;
keypad,num-columns = <1>;
nxp,debounce-delay-ms = <3>;
nxp,scan-delay-ms = <34>;
linux,keymap = <0x00000002>;
};
};
};
leds {
compatible = "gpio-leds";
......@@ -211,12 +71,31 @@ led1 { /* green */
};
};
/* Here, choose exactly one from: ohci, usbd */
&ohci /* &usbd */ {
transceiver = <&isp1301>;
&clcd {
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 0x59 0>;
reset-gpio = <&gpio 0x51 0>;
dac-clk = "wspll";
};
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c2 {
clock-frequency = <100000>;
};
&i2cusb {
clock-frequency = <100000>;
......@@ -225,3 +104,123 @@ isp1301: usb-transceiver@2c {
reg = <0x2c>;
};
};
&key {
keypad,num-rows = <1>;
keypad,num-columns = <1>;
nxp,debounce-delay-ms = <3>;
nxp,scan-delay-ms = <34>;
linux,keymap = <0x00000002>;
status = "okay";
};
&mac {
phy-mode = "rmii";
use-iram;
};
/* Here, choose exactly one from: ohci, usbd */
&ohci /* &usbd */ {
transceiver = <&isp1301>;
status = "okay";
};
&sd {
wp-gpios = <&gpio 3 0 0>;
cd-gpios = <&gpio 3 1 0>;
cd-inverted;
bus-width = <4>;
vmmc-supply = <&sd_reg>;
status = "okay";
};
/* 64MB Flash via SLC NAND controller */
&slc {
status = "okay";
nxp,wdr-clks = <14>;
nxp,wwidth = <40000000>;
nxp,whold = <100000000>;
nxp,wsetup = <100000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <40000000>;
nxp,rhold = <66666666>;
nxp,rsetup = <100000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
mtd0@00000000 {
label = "phy3250-boot";
reg = <0x00000000 0x00064000>;
read-only;
};
mtd1@00064000 {
label = "phy3250-uboot";
reg = <0x00064000 0x00190000>;
read-only;
};
mtd2@001f4000 {
label = "phy3250-ubt-prms";
reg = <0x001f4000 0x00010000>;
};
mtd3@00204000 {
label = "phy3250-kernel";
reg = <0x00204000 0x00400000>;
};
mtd4@00604000 {
label = "phy3250-rootfs";
reg = <0x00604000 0x039fc000>;
};
};
};
&ssp0 {
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
cs-gpios = <&gpio 3 5 0>;
status = "okay";
eeprom: at25@0 {
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
pl022,interface = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
at25,byte-len = <0x8000>;
at25,addr-mode = <2>;
at25,page-size = <64>;
};
};
&tsc {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart5 {
status = "okay";
};
arch/arm/boot/dts/lpc32xx.dtsi
View file @ 0d6cde50
......@@ -92,7 +92,8 @@ usb {
ohci: ohci@0 {
compatible = "nxp,ohci-nxp", "usb-ohci";
reg = <0x0 0x300>;
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&sic1>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
status = "disabled";
};
......@@ -100,10 +101,11 @@ ohci: ohci@0 {
usbd: usbd@0 {
compatible = "nxp,lpc3220-udc";
reg = <0x0 0x300>;
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
<62 IRQ_TYPE_LEVEL_HIGH>,
<60 IRQ_TYPE_LEVEL_HIGH>,
<58 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&sic1>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
<30 IRQ_TYPE_LEVEL_HIGH>,
<28 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_LOW>;
clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
status = "disabled";
};
......@@ -111,7 +113,8 @@ usbd: usbd@0 {
i2cusb: i2c@300 {
compatible = "nxp,pnx-i2c";
reg = <0x300 0x100>;
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&sic1>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -162,30 +165,44 @@ apb {
compatible = "simple-bus";
ranges = <0x20000000 0x20000000 0x30000000>;
/*
* ssp0 and spi1 are shared pins;
* enable one in your board dts, as needed.
*/
ssp0: ssp@20084000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x20084000 0x1000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SSP0>;
clock-names = "apb_pclk";
status = "disabled";
};
spi1: spi@20088000 {
compatible = "nxp,lpc3220-spi";
reg = <0x20088000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI1>;
status = "disabled";
};
/*
* ssp1 and spi2 are shared pins;
* enable one in your board dts, as needed.
*/
ssp1: ssp@2008c000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x2008c000 0x1000>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SSP1>;
clock-names = "apb_pclk";
status = "disabled";
};
spi2: spi@20090000 {
compatible = "nxp,lpc3220-spi";
reg = <0x20090000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI2>;
status = "disabled";
};
i2s0: i2s@20094000 {
......@@ -249,7 +266,8 @@ uart6: serial@40098000 {
i2c1: i2c@400A0000 {
compatible = "nxp,pnx-i2c";
reg = <0x400A0000 0x100>;
interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&sic1>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
#address-cells = <1>;
#size-cells = <0>;
pnx,timeout = <0x64>;
......@@ -259,7 +277,8 @@ i2c1: i2c@400A0000 {
i2c2: i2c@400A8000 {
compatible = "nxp,pnx-i2c";
reg = <0x400A8000 0x100>;
interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&sic1>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
#address-cells = <1>;
#size-cells = <0>;
pnx,timeout = <0x64>;
......@@ -294,22 +313,41 @@ clk: clock-controller@0 {
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
assigned-clock-rates = <208000000>;
};
};
/*
* MIC Interrupt controller includes:
* MIC @40008000
* SIC1 @4000C000
* SIC2 @40010000
*/
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
reg = <0x40008000 0x4000>;
interrupt-controller;
reg = <0x40008000 0xC000>;
#interrupt-cells = <2>;
};
sic1: interrupt-controller@4000c000 {
compatible = "nxp,lpc3220-sic";
reg = <0x4000c000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
<30 IRQ_TYPE_LEVEL_LOW>;
};
sic2: interrupt-controller@40010000 {
compatible = "nxp,lpc3220-sic";
reg = <0x40010000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
};
uart1: serial@40014000 {
compatible = "nxp,lpc3220-hsuart";
reg = <0x40014000 0x1000>;
......@@ -334,7 +372,8 @@ uart7: serial@4001c000 {
rtc: rtc@40024000 {
compatible = "nxp,lpc3220-rtc";
reg = <0x40024000 0x1000>;
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&sic1>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_RTC>;
};
......@@ -387,7 +426,8 @@ timer0: timer@40044000 {
adc: adc@40048000 {
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&sic1>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_ADC>;
status = "disabled";
};
......@@ -395,7 +435,8 @@ adc: adc@40048000 {
tsc: tsc@40048000 {
compatible = "nxp,lpc3220-tsc";
reg = <0x40048000 0x1000>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&sic1>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_ADC>;
status = "disabled";
};
......
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